Methods and apparatus employing an action engine for monitoring and/or controlling dynamic environments

ABSTRACT

A dynamic environment (e.g., an automated industrial process) has multiple conditions in response to which corresponding actions are required, and comprises various equipment, control device(s) to control the equipment, and one or more sensors to generate input signal(s) representing a monitored condition of the environment. A control system for the environment comprises a master processor and one or more co-processors, wherein the master processor configures a given co-processor to evaluate only a first subset of conditions expected to occur in the environment within a specified time period (e.g., less than a response time of the master processor), and to provide first control information representing an action to be taken if a particular condition of the first subset is satisfied. The co-processor receives the input signal(s) representing the monitored condition, processes the input signal(s) so as to determine if the particular condition of the first subset is satisfied, and provides the first control information to the control devices so as to control the equipment. Exemplary applications include dynamic environments in which machine vision techniques and/or equipment are employed.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims a priority benefit, under 35 U.S.C.§119(e), to U.S. provisional application Ser. No. 61/543,680, filed onOct. 5, 2011, entitled “Methods, Apparatus and Systems for Monitoringand/or Controlling Dynamic Environments,” which application isincorporated herein by reference in its entirety.

BACKGROUND

A programmable logic controller (PLC) is a special form ofcomputer-based controller typically employed to control equipment,machinery and/or instrumentation in automated industrialelectromechanical processes. A common example of such an automatedindustrial electromechanical process is given by the operation of afactory assembly line. In the dynamic environment of a factory assemblyline, there may be multiple pieces of industrial equipment, machineryand/or instrumentation (collectively referred to as “equipment” forsimplicity) associated with the fabrication, assembly, and/or packagingof parts/components, as well as the transport of the parts/componentsamongst various stages of fabrication, assembly and/or packaging.

FIG. 1 provides a general illustration of the typical role of aconventional PLC 50 in connection with an automated industrial process10 such as the operation of a factory assembly line. In addition tomultiple pieces of equipment 20, the dynamic environment of a factoryassembly line typically includes several control devices 30 (e.g.,actuators) for operating the multiple pieces of equipment 20, as well asmultiple input devices 40 (e.g., sensors) to provide indications ofequipment status and/or various conditions associated with fabrication,assembly, packaging and/or transport of parts/components. Suchindications provided by the input devices 40 often are referred to as“states” or “conditions” of the dynamic environment. Some examples ofcontrol devices 30 used to operate the equipment 20 include magneticrelays, solenoids, electric motors, and pneumatic or hydrauliccylinders. Some examples of input devices 40 include limit switches,position sensors, analog sensors (e.g., pressure or temperaturesensors), and imaging devices (e.g., cameras).

Generally speaking, the PLC 50 is employed to monitor input signals 66provided by input devices 40. These input signals, respectively or invarious combinations, represent different states (conditions) of thedynamic environment as a function of time. In response to the inputsignals present at a given time, the PLC 50 generates output signals 68to the control devices 30 for operating the industrial equipment 20, toensure the automated process 10 is implemented efficiently andpredictably. To this end, the PLC 50 generally is employed to coordinatepredetermined sequences of actions to be taken by the equipment 20implementing the process 10, in which respective actions may need tooccur within a certain time window contingent on information provided bythe input devices 40 (via the input signals 66).

A typical PLC includes programmable memory to store processor-executableinstructions and employs various other electronic components toimplement functions such as logic, sequencing, timing, counting, andarithmetic. In terms of general architecture and various aspects offunctionality, PLCs are in many respects similar to general-purposecomputers (e.g., desktop or laptop personal computers); however, whereasgeneral-purpose computers typically are optimized for calculation anddisplay tasks, PLCs generally are optimized for control tasks in adynamic environment such as an automated industrial process.Accordingly, PLCs generally are thought of as special-purpose controlcomputers for controlled dynamic environments. Since PLCs often areemployed in the demanding conditions of an automated industrial process,from a package design standpoint conventional PLCs often tend to beruggedly designed so as to withstand demanding environments in which thePLC may be exposed to one or more of physical vibrations, challengingtemperature and humidity conditions, dust or potentially damagingmaterials, and electrically noisy environments.

FIG. 2 illustrates a generalized block diagram of the typical electricalcomponents/circuitry (e.g., “hardware”) constituting the conventionalPLC 50 of FIG. 1. As shown in FIG. 2, the basic functional components ofthe PLC 50 include a processor unit 52, memory 54, power supply 56,input interface 58, output interface 60, and one or more communicationsinterfaces 62 all communicatively and/or electrically coupled to oneanother. FIG. 2 also shows a programming device 64 communicativelycoupled to the PLC 50 and employed to program the PLC.

In FIG. 2, the processor unit 52 includes a microprocessor to interpretinput signals 66 received by the input interface 58, and in turn provideoutput signals 68 via the output interface 60 so as to implement controlactions according to a program (e.g., series of processor-executableinstructions) stored in the memory 54. In particular, the memory 54stores the program containing instructions representing the controlactions to be implemented by the microprocessor, as well as various datarelating to input signals, output signals and operation of themicroprocessor as it carries out various instructions. The inputinterface 58 provides to the processor unit 52 information via inputsignals 66 received from external input devices (e.g., sensors,switches, meters, counters, etc.). The processor unit 52 in turncommunicates control actions to external output devices (e.g., valves,motors, etc.) via the output signals 68.

In FIG. 2, examples of components constituting the respective input andoutput interfaces may include analog-to-digital converters,optocouplers/optoisolators, buffers, latches, and drivers so as toappropriately interface with various external input and output devicesassociated with the controlled dynamic environment. Although four inputsignals and four output signals are shown for purposes of illustrationin FIG. 2, it should be appreciated that different types ofconventionally available PLCs may be configured to accept differentnumbers of input signals (some number N of input signals) and providedifferent numbers of output signals (some number X of output signal),and that the number of input signals and output signals need notnecessarily be the same. In general, the number N of input signals andthe number X of output signals is dictated at least in part by thenumber of input devices 40 employed to monitor the automated process 10of FIG. 1 and the number of control devices 30 employed to control theequipment 20.

In the PLC 50 shown in FIG. 2, the communications interface(s) 62 is/areused to receive and transmit various data (which may relate to one ormore of the programs for execution by the processor unit 52, the inputsignals, the output signals, other data to be utilized by the processorunit 52 in executing the program, etc.) via one or more communicationnetworks from or to one or more network-based external input/outputdevices and/or other remote PLCs. In general, the communicationsinterface(s) 62 implement such functions as device verification, dataacquisition, synchronization between user applications, and connectionmanagement. The power supply 56 converts AC voltage to a low DC voltage(e.g., 5 Volts) required for the various circuitry in the PLC tooperate. Finally, the programming device 64 (which in some examples maybe coupled to the PLC 50 via the communication interface(s) 62) isemployed to enter into the memory 54 the program to be executed by theprocessing unit 52; typically, the program is developed/written in theprogramming device 64 and then transferred to the memory 54 of the PLC50.

FIG. 3 provides additional details of the internal architecture of thePLC 50 shown in FIG. 2, particularly in connection with the processorunit, various elements of memory, input/output interfaces, and busses tofacilitate information transfer. For example, FIG. 3 illustrates thatthe processor unit 52 (denoted as CPU in FIG. 2) is associated with aclock 52A, the frequency of which determines the operating speed of thePLC and provides the timing and synchronization for various elements inthe PLC. Information within the PLC is carried amongst the processorunit, various memory elements, and to and from the input/outputinterfaces 58 and 60 via multiple busses; in particular, the PLC employsa data bus for transporting data to and from the PLC's constituentelements, an address bus to send the addresses of locations foraccessing stored data, and a control bus for signals relating tointernal control actions. The PLC architecture also may include an I/Osystem bus for communications between the input/output interfaces 58 and60 (from which the input signals 66 are received from external inputdevices, and the output signals 68 are provided to external outputdevices, respectively) and an input/output unit 55 configured totransfer input/output information between the I/O system bus and thePLC's data bus.

In general, the processor unit 52 (CPU) of the architecture shown inFIG. 3 includes an arithmetic and logic unit (ALU) that is responsiblefor data manipulation and carrying out arithmetic operations (e.g.,addition, subtraction, multiplication, division) and digital logicoperations (e.g., AND, OR, NOT, and EXCLUSIVE-OR), internal memoryregisters used to store information involved in program execution, andan internal control unit to receive the output of the clock 52A andcontrol the timing of operations. The various memory elementsconstituting memory 54 may include read-only-memory (ROM) 54A to providepermanent storage for the operating system and fixed data used by theprocessor unit, user program random-access memory 54B (User program RAM)employed for the program to be executed by the PLC, and datarandom-access memory 54C (Data RAM) used for data (information regardingthe status of input and output signals, values of timers and countersand other internal devices, etc.). The program to be executed by the PLCmay also be stored in non-volatile memory.

From the PLC architecture illustrated in FIG. 3, it may be appreciatedthat although conventional PLCs often are considered special-purposecomputers rather than general-purpose computers, both PLCs andgeneral-purpose computers share many aspects of a “Von Neumann” computerarchitecture. In a Von Neumann computer architecture, computerinstructions (the “user program” stored in User program RAM 54A) as wellas any data required for program execution (e.g., stored in Data RAM54C) are accessed from various memory elements over a common busarchitecture (i.e., via the address, data and control busses shown inFIG. 3). Although conventional PLCs attempt to tailor computerperformance by being special-purpose computing devices implementingspecific functionality corresponding to a particular automatedindustrial process, the architecture of conventional PLCs nonethelessplaces fundamental limits on their performance, as they executeinstructions serially and hence effectively have no capacity forparallel execution.

Programming of a PLC primarily is concerned with specifying digitallogic functions that process one or more input signals representing asensed condition (“state”) associated with the automated process beingimplemented by various equipment at a given time. The digital logicfunctions acting on the monitored condition of the automated processgenerate one or more control signals in response to the monitoredcondition. As noted above, these control signals are applied to controldevices that in turn control the various equipment to take some actioninvolved in further implementing the automated process. At a high level,a PLC program generally implements a sequence of one or more actions inresponse to monitored conditions as a function of time (e.g., if A or Boccurs, actuate C; if A and B occurs, actuate D). The automated processevolves over time as actuators control equipment to drive the process tonew conditions. Hence, as noted above, the automated process constitutesa dynamic environment in which an evolution of conditions is monitoredby the PLC, and wherein the PLC makes decisions and updates controlsignals to actuators, based on respective monitored conditions, to drivethe environment to new conditions.

Many conventional PLCs are programmed via a “ladder logic” programminglanguage to codify the digital logic that is used to evaluate inputssignals representing monitored conditions. Common ladder logicprogramming languages typically employ graphical diagrams that resemble“rungs” of a ladder, wherein respective rungs represent circuit diagramsfor electromechanical relays (which were used in older logical controlsystems) to facilitate intuitive programming by control systemengineers. Ladder logic is best suited to implement control solutions inwhich primarily binary variables are involved (e.g., the monitoredconditions in a dynamic environment each may be represented as TRUE,i.e., logic one, or FALSE, i.e., logic zero).

However, in a variety of automated process environments, outputs ofsensors may be analog signals. Accordingly, in some instances, if thedirect output of a given input device/sensor is not in the form of abinary signal, the output of the input device/sensor may bepre-conditioned in some respects to provide the input signals 66 inbinary form. For example, an analog output of a temperature sensingdevice may be first applied to a comparator circuit having a temperatureset point voltage as another input so as to provide, as one of the inputsignals 66, a binary indication of whether or not the monitoredtemperature is above or below the particular temperature set point.Alternatively, an analog value may be converted to a quantitative valueencoded into a multi-bit digital word used by the system to performmathematical operations and/or make decisions. Similarly, a multi-bitoutput of a counter serving as an input device may be compared to apre-determined count to in turn provide, as one of the input signals 66,a binary indication of whether or not the counter output is above orbelow the pre-determined count (alternatively, an output of a counterhaving some number B of bits may be provided directly as a number B ofinput signals 66). Yet other types of input devices may generate highlytransient signals; for such devices, a latch may be employed tofacilitate the detection of a signal edge or transient so as to providean input signal of suitable duration to the PLC indicating theoccurrence of the edge/transient. In other examples, input devices mayinclude various networked devices, for which one or more communicationstatus signals (e.g., data packet transmitted/received) may serve as oneof the input signals 66.

Ladder logic and other languages for programming conventional PLCsgenerally are considered to be rules-based programming languages. Atypical PLC program may be constituted by a series of rules, whereineach rule is constituted by one or more binary input signals (e.g., A,B, C, D) representing a monitored condition of the automated process,and a corresponding control signal (e.g., X) that is generated inresponse to particular digital logic evaluating the input signals.Accordingly, in some aspects a rule in a PLC program may be viewed in amanner similar to an “IF/THEN” statement (e.g., If (A AND NOT B) AND (COR D), THEN X). The PLC program includes all of the rules necessary toimplement all of the actions that are required in response to differentcombinations of input signals representing all of the different possibleconditions of the automated process that may be monitored via the set ofavailable input signals.

With reference again to FIG. 2, the programming device 64 (which may bea handheld programming device, a desktop console, or a personal computersuch as a laptop or tablet computer) is typically employed to create,store and download to the PLC executable programs including a set ofrules. When the program is executed by the PLC, the rules are typicallyexecuted sequentially from first to last and then repeated, wherein eachpass through the set of rules in sequence often is referred to as a“scan” or “control loop.” Thus, consecutive repetitions of the scan orcontrol loop represent a continuous cycle of the PLC reading inputsignals, examining input signal using the logic encoded in the programrules, and then changing control signals output by the PLC asappropriate.

More specifically, with respect to general operation, including varioushousekeeping activities and performing scans or control loops,conventional PLCs typically function in a cyclical manner. For example,when power is initially applied to a PLC, the PLC may perform aself-check or diagnostic routine to ensure that various hardwarecomponents are functioning properly. With reference again to FIGS. 2 and3, if no fault or error conditions are detected, the PLC then controlsthe input interface 58 and memory 54 so as to read each of the inputsignals 66 sequentially and store each read instance of a given inputsignal in a dedicated memory location. The PLC then executes its programby sequentially testing each rule (i.e., fetching, decoding andexecuting the program instructions in sequence) and solving the logicencoded in the rule.

In particular, for each rule, the stored instances of certain inputsignals as specified in the rule are retrieved from memory, the rule isevaluated based on the retrieved input signals, and if the rule issatisfied (i.e., all of the pre-requisite conditions specified in therule are met), a control signal corresponding to the satisfaction of therule is generated. If such a control signal is generated, it is storedin a dedicated memory location. Evaluation of a given rule may involvemultiple read operations from, and write operations to, different memorylocations (e.g., registers) as the digital logic codified in the rule issolved. As noted above, respective rules are evaluated sequentially asthe PLC executes the ladder logic program; accordingly, while the PLC isevaluating a particular rule, it is inattentive to the other rulescodified in the program.

If the PLC generates any control signals in response to evaluation ofthe rules, it may provide these for output as a set of updated controlsignals 68. These control signals in turn are transmitted to one or moreactuators or other equipment to be controlled in connection with theautomated process. The PLC then returns to performing the self-check,reading each of the input signals and storing them to memory, executingthe program rules to complete the control loop, updating the controlsignals for output (if any), and repeating this cycle iteratively.

The time period required by the PLC to complete the cycle describedabove commonly is referred to as a “cycle time” or “scan time.” Typicalcycle times of conventional PLCs are on the order of approximately 10milliseconds to hundreds of milliseconds. The cycle time generally isdetermined by the particular CPU used in the processor unit, the size ofthe program to be scanned (e.g., the number of rules constituting theprogram, which in turn depends at least in part on the number of inputsignals to be read, the number of input signal combinations for whichindependent evaluations are required, and the number of control signalsto be generated), and the system functions that are in use pursuant toexecution of the program. Thus, the more complex the program, the longerthe cycle time will be.

It should be appreciated that, in a conventional PLC, the vast majorityof rules when evaluated in a given cycle are not satisfied (i.e., nocontrol signal is generated pursuant to evaluation of the rule); if arule is not satisfied, the program merely moves to the next rule forevaluation. In this manner, it is common in conventional PLCs for asubstantial portion of a given cycle to be spent evaluating successiverules without generating any control signals.

Although relatively quick compared to general-purpose computersprogrammed to implement similar functionality, the cycle time of a PLCis not instantaneous. As a result, the PLC does not “watch” its inputsignals all of the time, but instead the PLC samples the states of theinput signals periodically depending on the cycle time. Furthermore, thecycle time constitutes a minimum delay in updating control signals (ifgenerated pursuant to a satisfied rule) that are output by the PLC inresponse to sampled input signals. In this manner, the cycle time alsomay be viewed as a minimum response time (a “reaction time”) of the PLCto a particular monitored condition (i.e., represented by a particularvalue for one or more of the input signals), and is often referred to asa “latency” of the PLC. Thus, it should be appreciated that due to thislatency, an input signal that lasts for a duration shorter than thecycle time may be missed by the program (in general, any input signalmust be present for longer than the cycle time). In some instances,external circuitry may be employed to latch transient signals so thatthey will not be missed entirely by the PLC. Even if a particular inputsignal is not “missed” due to latching, however, a control signal thatis to be generated in response to the input signal may be generated bythe PLC too late to be effective for the correct operation of theequipment being controlled.

Because of the cyclical nature in which a conventional PLC executes aprogram, all possible combinations of input signals (representing allpossible conditions of the automated process being controlled for whichsome action is required) must be contemplated in a single control loopof the program. Stated differently, as noted above, as long as amonitored condition represented by one or more input signals is in somemanner involved in causing some action to occur (via one or more controlsignals) at some point during the duration of an automated process,there needs to be one or more rules in the program that evaluate theparticular monitored condition. As noted above, the latency of aconventional PLC scales with program complexity; hence, as the number ofpossible conditions of the process for which actions are requiredincreases, the program becomes larger and the latency becomes greater.Furthermore, in many automated processes, some conditions occur morefrequently than others, and in some instances conditions that may occurrarely may be associated with a rule representing complicated logic thatneeds to be evaluated (which requires more processing time).Accordingly, significant portions of the cycle time may be “used up”(and latency exacerbated) by executing one or more rules to evaluate oneor more monitored conditions that occur rarely.

SUMMARY

The Inventors have recognized and appreciated that typical latenciesassociated with conventional programmable logic controllers (PLCs) maybe excessively long for monitoring and/or controlling some types ofdynamic environments (e.g., involving automated systems and/orprocesses). More generally, conventional PLCs as well as other moregeneral-purpose computers often are not appropriately suited forapplications involving monitoring and/or controlling dynamicenvironments in which significant speed and/or precision is/are requiredin connection with response or reaction time (e.g., taking some action,such as controlling equipment, machinery and/or instrumentation, inresponse to one or more monitored conditions).

In particular, processor-based control devices employing ageneral-purpose computer architecture (or related computer architectureswith a small and finite set of general purpose processors), andexecuting programs sequentially or cyclically, are not sufficiently fastto implement control functions in dynamic environments that requirereflex-like reactions in response to evolving conditions of theenvironment, which may benefit from essentially simultaneous evaluationof multiple possible conditions and taking immediate action based onsame. Examples of dynamic environments requiring reflex-like reactionsinclude, but are not limited to, aircraft control, complex chemicalprocess control, and machine vision applications (e.g., analysis ofimages to extract data for controlling various processes, such asautomatic inspection and robot guidance).

In view of the foregoing, various inventive embodiments described hereinare directed to methods, apparatus and systems for monitoring and/orcontrolling dynamic environments, in which reactions to evolvingconditions of the environment may be provided with significantly lowerlatency and/or lower variability latency than possible with conventionalPLCs and/or other conventional computing devices.

For purposes of the present disclosure, a “dynamic environment” refersto a process and/or system, whether implemented physically and/orvirtually (e.g., for purposes of simulation), in which a condition ofthe process and/or system (also referred to herein as a “state” of theenvironment) may be monitored as a function of time, and one or moreactions may be taken (e.g., in the form of control stimuli applied tothe process and/or system) in response to a particular condition orevolution of conditions. In exemplary implementations discussed ingreater detail below, actions taken in response to a particularcondition or evolution of conditions of the dynamic environment may be“reflexive” in nature, in that they are nearly instantaneous as a resultof the appreciably low latency achieved by the inventive methods,apparatus and systems disclosed herein. While many practicalapplications of the concepts disclosed herein are contemplated forphysical implementations of automated industrial control processes andsystems, for example, it should be appreciated that the inventiveconcepts disclosed herein are not limited in this respect, and may beapplied advantageously in a variety of physical and/or virtual dynamicenvironments.

In connection with achieving appreciably low latency for controlling adynamic environment, the Inventors have recognized and appreciated thatfor a given dynamic environment, different conditions requiring actionmay occur on different time scales and/or within different time frames(e.g., some conditions may occur more often than others, and/or in closetemporal proximity with certain other conditions). Furthermore, someconditions may occur more often in particular sequences, and/or as aresult of one or more particular actions previously having been taken.Accordingly, in one aspect of some inventive embodiments describedherein, rather than considering the entire dynamic environment as awhole and contemplating all possible conditions of the dynamicenvironment over all time for which actions may be required, theInventors have recognized and appreciated that by breaking up thedynamic environment into multiple sub-environments (e.g., sub-processesand/or sub-systems) based on a variety of criteria (e.g., timescale/time frame, particular patterns of evolution or change incondition), a control methodology may be implemented with significantlylow latency. Stated differently, the Inventors have recognized that byidentifying particular categories of conditions that can occur andcorresponding required actions that may be taken in a dynamicenvironment (e.g., a subset of conditions that could all occur within acertain time period, a subset of conditions that could only occur aftera particular action was taken, etc.), the control solution may besubdivided and shared amongst multiple assessment and control resourcesto significantly reduce latency.

With the foregoing in mind, some embodiments of the present inventionrelate to a control system for a dynamic environment (e.g., as areplacement for the conventional PLC 50 shown in FIG. 1), wherein thecontrol system employs a “master” processor (also referred to herein asa “housekeeping” processor) and one or more independent (i.e.,asynchronous) “slave” co-processors (also referred to herein as“responsive” co-processors) each dedicated to evaluating one or moreconditions constituting a subset of all possible conditions that need tobe evaluated in a given dynamic environment. The subset of conditionsfor which a given co-processor in the control system is tasked toevaluate may be based on a number of different criteria, as noted above(e.g., time scale/time frame, particular patterns of evolution or changein condition). For purposes of the present disclosure, “evaluating” acondition refers to determining the presence of the condition(“satisfying” the condition, e.g., by comparing some number N ofmonitored input signals at a given time to particular input signalvalues representing the condition) and taking appropriate action inresponse to the condition (e.g., generating one or more correspondingcontrol signals, or particular instructions for generating same).

Such a control system including a master “housekeeping” processor andone or more slave “responsive” co-processors respectively dedicated toevaluating some subset of conditions in a dynamic environment may beviewed as adopting a “divide and conquer” approach to monitoring andcontrolling the dynamic environment. In particular, rather thanemploying a single processor to evaluate all possible conditions of theenvironment for which actions are required, the master processor maytask one or more co-processors to evaluate only some subset of possibleconditions for which actions are required, thereby relieving the masterprocessor of significant processing burden. In this manner, the latencyof the entire control system is a function of co-processor latency(e.g., if multiple co-processors are employed, the latency of thecontrol system as a whole may be a function of the largest co-processorlatency).

By distributing the condition evaluation process for the dynamicenvironment amongst multiple co-processors in the foregoing fashion, thelatency of the control system as a whole may be significantly reduced(e.g., in some cases by several orders of magnitude) as compared toconventional control approaches employing a single PLC and/orgeneral-purpose computer. In various implementations discussed ingreater detail below, not only is appreciably low control system latencyrealized by such a “divide and conquer” approach, but predictable andrepeatable latencies also may be realized with exemplary control systemand/or co-processor architectures. One or both of low latency and lowvariability latency may be particularly advantageous in some machinevision applications, in which reliable/predictable machine behavior,including acquisitions of images correctly synchronized with machine andlighting system operation, is important. Low latency and low variabilitylatency also may be important for coordinating control activities asindicated above with decisions resulting from computer analysis that maytake place in a different time domain.

In one embodiment of a control system according to the presentinvention, a master processor (e.g., which in some cases may beimplemented as a general-purpose computer) is communicatively coupled toone or more slave co-processors. Each slave co-processor includes itsown dedicated memory (i.e., not shared with other co-processors, if theyare present, and accessible only to the co-processor itself and themaster processor), as well as associated hardware (e.g., processingand/or logic circuitry) to act on the contents of the dedicated memory.The contents of a given co-processor's dedicated memory may be provided(i.e., loaded into the co-processor) by the master processor. Inexemplary system architectures discussed in greater detail below, insome aspects a given slave co-processor also has substantiallyunfettered access to input signals representing different conditions ofa dynamic environment, as well as communication paths (e.g., with themaster processor and the dynamic environment), such that multipleco-processors are capable of monitoring the same set of input signals atthe same time and evaluating their associated conditions based on thesame set of input signals.

In one exemplary implementation, the contents of the co-processor'sdedicated memory includes information (e.g., a program) relating toevaluation of a single condition of the dynamic environment; hence, insuch an implementation, a given co-processor is configured (e.g., toexecute the program stored in the dedicated memory, or otherwiseimplement particular digital logic functions on the memory contents) toevaluate only the single condition of the dynamic environment pursuantto the particular information stored in the co-processor's dedicatedmemory (in other embodiments discussed below, a co-processor may beconfigured to evaluate multiple conditions). When a slave co-processordetermines that its condition is present, it takes the correspondingprescribed action according to the co-processor's program/logic (e.g.,the co-processor provides some output that in turn generates one or morecontrol signals as appropriate) and notifies the master processor thatits condition is satisfied. In other implementations, rather than theco-processor itself taking the corresponding prescribed action, theco-processor may merely notify the master processor that its conditionis satisfied (e.g., by generating an interrupt to the master processor),and the master processor in turn may be appropriately configured to takethe corresponding prescribed action. In either situation, by“offloading” from the master processor at least the evaluation of thecondition, the co-processor significantly improves the response time ofthe control system as a whole.

In some embodiments discussed in further detail below, in response to anotification from a co-processor that its condition is satisfied, themaster processor may “re-task” the co-processor by loading into theco-processor's dedicated memory new information relating to a newcondition to evaluate (and corresponding action to be taken if the newcondition is satisfied). In this manner, the master processorfacilitates effective control of the dynamic environment as it evolvesover time by dynamically re-tasking one or more co-processors of thecontrol system (to evaluate new conditions and/or take new/differentactions).

In some implementations of a control system according to the presentinvention, multiple slave co-processors may be employed if there aremultiple conditions to be evaluated in the dynamic environment within agiven time frame, such that respective co-processors are configured toevaluate different possible conditions and take appropriate action asnecessary. In one aspect of such an implementation, the set of Navailable input signals representing different possible conditions ofthe dynamic environment may be provided identically (e.g., in parallel,via a bus architecture) and available simultaneously to all of theco-processors for evaluation. Accordingly, the respective co-processorsindependently (i.e., asynchronously) may monitor the set of N availableinput signals, evaluate their respective conditions, take action if/asappropriate, and notify the master processor when their conditions aresatisfied. In this manner, as noted above, the latency of the controlsystem is a function of a given co-processor's latency. In situations inwhich a co-processor is configured to evaluate a single condition, notonly is the latency of the co-processor appreciably low, but the latencyvariation is appreciably low as well (and, for many practical purposes,substantially zero).

A variety of co-processor implementations are contemplated according tovarious embodiments of the invention. For example, in one embodiment, aco-processor may be implemented as a full-featured processor running anappreciably short program loaded in its dedicated memory (e.g., a singleIF THEN statement inside a loop for evaluating a particular condition).In this type of co-processor implementation, typical latencies for theco-processor (based on conventional processors evaluating a relativelysmall number of instructions representing the IF THEN loop) may be onthe order of about one microsecond. For applications in which spaceand/or hardware costs may be important practical considerations,however, the implementation of a co-processor as a full-featuredprocessor, particularly if control of a dynamic environment entailsevaluation of numerous conditions and implicates multiple co-processorsin a control system, may be impractical in some instances (e.g., theprocessing resources being spent on evaluating a single condition may begreater than necessary, and may take up excessive chip space).

In view of the foregoing, in other co-processor implementationsaccording to various embodiments of the invention, a significantlystreamlined special-purpose co-processor includes pared-down digitallogic to specifically implement a comparator function (e.g., thefunctional equivalent of an IF THEN statement) based on the contents ofthe co-processor's dedicated memory and the monitored input signals; inessence, the functional capability of the co-processor is reduced to theparticular evaluation of a single condition via a significant reductionin hardware. Such a co-processor implementation accomplishes the goal ofa low-cost, space-saving, low-latency solution. In exemplaryimplementations, several such co-processors may be implementedinexpensively in a field programmable gate array (FPGA), an applicationspecific integrated circuit (ASIC), or a fully-customized circuit, forexample.

In one aspect of a streamlined co-processor implementation as discussedabove, to alternatively or further facilitate low latency, a particularmemory structure is employed for the co-processor's dedicated memory tostore information in the form of a “condition/action pair.” In oneexample of such a memory structure, a condition/action pair comprisesparticular data stored in a memory location (e.g., a single memoryregister, or multiple adjacent memory registers) arranged as a firstnumber of bits representing the condition to be evaluated, and a secondnumber of bits representing an action to be taken if the condition issatisfied. Such a memory structure facilitates a straightforward andrelatively simple digital logic implementation to compare monitoredinput signals to the first number of bits representing the condition tobe evaluated and, if there is a match (i.e., the condition issatisfied), provide the second number of bits representing thecorresponding action to be taken as a gated output of the co-processor.Accordingly, based on structured memory contents constituting a“condition/action pair” and relatively simple digital logic implementinga comparator and a gate to provide a gated output, and effectivelow-latency, low-footprint, and low-cost co-processor may be realized.

The configuration of a control system in which each co-processor istasked with evaluating only a single condition (i.e., the smallestsubset) of all possible conditions for the dynamic environment may beviewed as a “degenerate” case of minimum latency for the control system.More generally, the latency for the control system is dictated by thephysical implementation of a given co-processor in the control system(e.g., full-featured microprocessor vs. pared-down simplified digitallogic implementation), and/or the functions (e.g., programmed logicfunctions) being implemented by the co-processor. As discussed below, insome embodiments the physical implementation and/or the functionsimplemented by a co-processor are particularly designed such that anupper bound on a latency of the co-processor is below a requiredresponse time for the condition(s) being evaluated by the co-processor.In some cases, meeting such a requirement may require that theco-processor only be configured to evaluate a single condition, while inother cases the co-processor may be configured to evaluate a subset ofsome predetermined number of conditions (e.g., sequentially rather than“simultaneously,” but on a purposefully limited number of conditions).In general, by purposefully limiting the function of the co-processor(e.g., size of the program executed by the co-processor and/or theinformation to be processed), an upper bound on latency may beessentially guaranteed.

Based on the foregoing premise of purposefully limiting the function(s)of a given co-processor, some implementations of a control systemaccording to various embodiments of the present invention may bepredicated at least in part on appropriately balancing the followingdesign constraints in the context of controlling a particular dynamicenvironment: 1) ensuring that the co-processor is configured to evaluatea sufficiently comprehensive subset of conditions that may be present inthe dynamic environment pursuant to some criteria (e.g., within aparticular time frame, in a particular sequence, following previousparticular actions being taken, etc.); 2) ensuring that the co-processorhas sufficiently low (but not necessarily minimum achievable) latency totake action in response to satisfied conditions in an appropriate timeframe (i.e., ensuring that there is a predictable and sufficiently lowupper bound on the co-processor's latency); and 3) ensuring thatrealization of the co-processor entails reasonably low hardware costsand/or space requirements.

In view of the foregoing, some embodiments of the present invention aredirected to a control system that includes an “action engine” that maycomprise one or more co-processors, wherein a given co-processor of theaction engine may be configured to evaluate a particular subset ofmultiple conditions that may arise in a dynamic environment. In oneimplementation of an action engine including multiple co-processors,each co-processor may function autonomously and simultaneously evaluateat any given time one or more particular conditions represented by somenumber N of input signals being monitored at the same time by allco-processors of the action engine.

In another implementation of an action engine according to oneembodiment, the action engine is configured to evaluate up to some fixedmaximum number of conditions so as to establish an upper bound onlatency and ensure sufficiently low variation in latency. To this end,in one example an action engine comprises an “event table” realized by amemory structure that includes some number of multiplesequentially-indexed memory locations (e.g., registers, or contiguousgroups of registers) each having a particular size. In one aspect, eachsuch memory location is configured to store information in the form of a“condition/action” pair as discussed above, e.g., some first number ofbits representing a condition to be evaluated, and some second number ofbits representing some action to be taken if the condition is satisfied.In another aspect, respective memory locations of the event table storedifferent condition/action pairs such that a given memory location inthe event table is “dedicated” to evaluating a particular condition thatmay be represented by the N input signals.

In the foregoing example, the action engine further may include a“scanner,” communicatively coupled to the event table and configured toreceive the N input signals, to sequentially evaluate the conditionsrepresented by the condition/action pairs stored in the respectivememory locations of the event table. To this end, the scanner includesappropriate digital logic circuitry (e.g., logic gates to implement acomparator and a gated output) to read the contents of a given memorylocation and compare the condition portion of the condition/action pairto the respective values of the N input signals. In one example, thecondition portion of the condition/action pair includes N bits of theoverall information stored in the given memory location, such that thereis a one-to-one correspondence between the condition portion of thecondition/action pair and the N input signals. Regardless of whether ornot the particular condition is satisfied (i.e., the respective valuesof the N input signals do or do not match the condition portion of thecondition/action pair), the scanner proceeds to reading the contents ofthe next memory location in the event table so as to compare thecondition portion of the condition/action pair stored in the next memorylocation to the respective values of the N input signals.

If a particular condition represented by the condition portion of acondition/action pair stored in a given memory location of the eventtable is satisfied (i.e., the respective values of the N input signalsmatch the condition portion of the condition/action pair), the scannerprovides as an output the action portion of the condition/action pair(e.g., as a gated output enabled by a comparator upon a match). Thisoutput itself may constitute one or more control signals, or representan instruction that in turn generates one or more control signals, forcontrolling equipment in the dynamic environment. The scanner thenproceeds to reading the contents of the next memory location in theevent table so as to compare the condition portion of thecondition/action pair stored in the next memory location to therespective values of the N input signals and, if there is a match, thescanner provides the action portion of the condition/action pair as agated output. Once the scanner reaches the last memory location of theevent table and appropriately processes the condition/action pair storedin this last memory location, the scanner returns to the first memorylocation in the event table and repeats the cycle of sequentiallyprocessing the contents of successive memory locations of the eventtable.

In some embodiments, an action engine including an event table andscanner as described above may be communicatively coupled to a master(or “housekeeping”) processor that provides the contents of the eventtable (e.g., the condition/action pairs, and possibly other information)and oversees the appropriate mapping of particular condition/actionpairs to particular memory locations of the event table (e.g., based ona particular order or sequence in which the master processor wants theaction engine to process the condition/action pairs). In one aspect, themaster processor may occasionally or periodically “re-task” the actionengine by loading one or more new condition/action pairs into its eventtable for processing by the scanner of the action engine. To this end,the scanner may provide an indication to the master processor that thecondition corresponding to a particular condition/action pair beingprocessed is satisfied, in response to which indication the masterprocessor may load one or more new condition/action pairs into the eventtable. Such an indication of a satisfied condition may be constituted bythe generation of the output itself representing an action to be taken(which output may be monitored by the master processor), or in the formof a separate status signal or interrupt generated by the action engineand monitored by the master processor. Additionally (or alternatively),the scanner may provide an indication to the master processor that afull scan of the event table is complete (e.g., after processing of thecondition/action pair stored in the last memory location of the eventtable), at which point the master processor may reload the event tablewith one or more new condition/action pairs, or a complete new set ofcondition/action pairs, for processing during a subsequent scan of theevent table by the scanner.

In embodiments of a control system according to the present inventionthat include a master processor and an action engine as described above,in one aspect the housekeeping and “re-tasking” functions accomplishedby the master processor facilitate a “divide and conquer” approach tocontrolling a dynamic environment, as discussed earlier. In particular,in some implementations, given some total number T of possibleconditions for which corresponding actions may be required in a dynamicenvironment, the master processor is configured (e.g., programmed) toselect only a particular subset of the total number T of possibleconditions, and task the action engine at a given time to evaluate onlythis particular subset of conditions. As noted above, the masterprocessor may be programmed to make the selection of a particular subsetof conditions for evaluation by the processor based on various criteria.In one example, the master processor selects a subset of conditions forevaluation by the action engine based at least in part on a time periodin which the subset of conditions is expected to occur in the dynamicenvironment, and in consideration of the response time (e.g., longest or“worst-case” response time) of the master processor itself in attendingto its various duties (e.g., monitoring and/or controlling functions forwhich the master processor itself may be tasked in the overall contextof the dynamic environment).

For example, in carrying out its own duties in the context of a givendynamic environment, the master processor itself has a limit on itsability to receive, process, and respond to information within a certaintime period. In particular, a general purpose computer serving as themaster processor is subject to various scheduling constraints (e.g.,pursuant to scheduling and dispatching software) that governs the mannerin which multiple processes that need to be attended to by the processorare assigned to execute. Given the serial nature in which processes needto be scheduled, there is necessarily some lag time, or “response time”of the master processor, representing an amount of time between arequest to initiate a given process and providing some response pursuantto execution of that process. The response time of the master processortypically is based at least in part on the number of such processes thatneed to be scheduled in order for the master processor to attend to itsrequired functions in the context of the dynamic environment, as well asthe complexity of the respective processes being scheduled. In somerespects, this situation is similar to that of a conventional PLC, inwhich the scan time or cycle time of the PLC is based on the number andcomplexity of rules encoded in the PLCs program, which placesfundamental limits on the ability of the PLC to provide control signalswithin a particular time frame in response to monitored conditions.

The response time of the master processor may have some nominal expectedor typical value, based at least in part on the number of respectiveprocesses that need to be scheduled and the complexity of thoseprocesses (which in turn is dictated at least in part by therequirements of the dynamic environment being monitored and controlled,and the complexity of control tasks at hand). Given the variability offunctions potentially performed by the master processor in a givendynamic environment, however, there is typically a longest potentialresponse time, or a “worst-case” response time, to which the masterprocessor may be subject in processing information. If there areconditions of the dynamic environment (for which actions may berequired) that may occur within a time period that is shorter than theworst-case response time of the master processor, the master processoritself effectively would be incapable of reliably responding to theseconditions. Accordingly, the longest potential response time or“worst-case” response time of the master processor in the context of agiven dynamic environment may serve as one example of a criterion uponwhich the master processor may select a subset of conditions forevaluation by the action engine. In this manner, the master processoressentially charges the action engine with “paying attention” tomonitoring certain conditions of the dynamic environment during a timeperiod in which the master processor effectively is incapable of doingso itself.

Stated differently, based on at least the criterion of time scale/timeframe in which certain conditions may be expected in the dynamicenvironment, the master processor selects a subset of conditions thatcould arise in the dynamic environment during a time periodcorresponding to a worst-case response time of the master processor, andloads condition/action pairs into the action engine for processingduring that time period. During that time period, the action engine maycomplete many hundreds or even thousands of scanning cycles beforeidentifying that a particular condition represented in the actionengine's event table is satisfied. Once the conditions are evaluated,appropriate action taken if/as necessary, and the master processor isagain able to correspond with the action engine (i.e., within theworst-case response time of the master processor), the master processormay load one or more new condition/action pairs into the action engine'sevent table, for evaluation during the next time period during which themaster processor may be preoccupied with other tasks (other scheduledprocesses). In one aspect, the newly loaded condition/action pairs maybe based at least in part on the previously evaluated conditions andactions taken, if any. In this manner, the master processor isresponsive to an evolution of conditions in the dynamic environment, andoffloads significant processing burden to the action engine byrepeatedly re-tasking the action engine to evaluate, at any given time,only a subset of conditions that are expected to occur within aparticular time period (e.g., corresponding to the response time of themaster processor).

In the foregoing example of an action engine, it should be appreciatedthat in one aspect, the combination of a dedicated memory location ofthe event table storing a particular condition/action pair, when coupledto the digital logic circuitry of the scanner to evaluate the condition(and, if satisfied, provide an output representing the action to betaken), is functionally equivalent to a co-processor as discussed abovededicated to evaluating a single condition. However, rather than onlyevaluating a single condition, the configuration of the scanner allowsthe digital logic circuitry performing the evaluation to be “shared”(e.g., in a scanned or time division multiplexed manner) amongst therespective memory locations of the event table, such that thecombination of the scanner and the event table of the action engineessentially constitutes a co-processor configured to evaluate multipleconditions and take action as appropriate. Such a component arrangementfacilitates efficient and conservative use of hardware resources.

In various aspects, the size (e.g., number of bits) of the respectivememory locations in an event table of the action engine, the totalnumber of dedicated memory locations in the event table, and theconfiguration of the scanner itself (e.g., the digital logic implementedby the scanner) are specified so as to achieve a desired latency forcontrol of a particular dynamic environment, wherein the latency has asufficiently low upper bound and/or sufficiently predictable (and insome cases insubstantial) variation. In one particular implementationdiscussed in greater detail below, an appropriately configured actionengine based on an event table and a scanner achieves a latency for theaction engine on the order of 10 nanoseconds per condition/action pair(e.g., based on a 100 MHz clock driving the logic functionality of thescanner); accordingly, for an event table having 128 memory locationsrespectively storing 128 condition/action pairs, for example, an actionengine latency on the order of approximately 1.28 microseconds (128×10nanoseconds) may be realized. Such a latency metric is several orders ofmagnitude lower than the typical latency of tens to hundreds ofmilliseconds observed in conventional PLCs.

It should be appreciated that all combinations of the foregoing conceptsand additional concepts discussed in greater detail below (provided suchconcepts are not mutually inconsistent) are contemplated as being partof the inventive subject matter disclosed herein. In particular, allcombinations of claimed subject matter appearing at the end of thisdisclosure are contemplated as being part of the inventive subjectmatter disclosed herein.

BRIEF DESCRIPTION OF THE DRAWINGS

The skilled artisan will understand that the drawings primarily are forillustrative purposes and are not intended to limit the scope of theinventive subject matter described herein. The drawings are notnecessarily to scale; in some instances, various aspects of theinventive subject matter disclosed herein may be shown exaggerated orenlarged in the drawings to facilitate an understanding of differentfeatures. In the drawings, like reference characters generally refer tolike features (e.g., functionally similar and/or structurally similarelements).

FIG. 1 is a general illustration of the typical role of a conventionalprogrammable logic controller (PLC) in connection with an automatedindustrial process.

FIG. 2 is a generalized block diagram of the typical electricalcomponents/circuitry (e.g., “hardware”) constituting the conventionalPLC of FIG. 1.

FIG. 3 is a block diagram that shows additional details of the internalarchitecture of the conventional PLC shown in FIG. 2, particularly inconnection with the processor unit, memory, and input/output interfaces.

FIG. 4 is a block diagram illustrating a control system for monitoringand controlling a dynamic environment, wherein the control systemincludes a master processor communicatively coupled to an action enginecomprising one or more co-processors, according to one embodiment of thepresent invention.

FIG. 5 is a block diagram of an action engine that includes multipleco-processors that operate in parallel to monitor, synchronize, and/orcontrol at least one aspect of a dynamic environment, according to oneembodiment of the present invention.

FIG. 6 is a block diagram of an action engine that includes an eventtable and a scanner that operate to monitor, synchronize, and/or controlat least one aspect of a dynamic environment, according to oneembodiment of the present invention.

FIG. 7 is a block diagram of a scanner suitable for use in the actionengine of FIG. 6, according to one embodiment of the present invention.

FIG. 8 is a diagram that illustrates the use of chained registers in theevent table of FIG. 6, according to one embodiment of the presentinvention.

FIG. 9 is a block diagram of an action engine that includes multipleco-processors, each of which includes an event table and a scanner, thatare configured to respond to operate in parallel to control at least oneaspect of a dynamic environment, according to one embodiment of thepresent invention.

FIG. 10 is a block diagram of a dynamic environment in which machinevision techniques and equipment are employed, as well as a controlsystem according to one embodiment of the present invention, formonitoring and controlling the dynamic environment.

DETAILED DESCRIPTION

Following below are more detailed descriptions of various conceptsrelated to, and embodiments of, inventive systems, methods and apparatusfor monitoring and/or controlling dynamic environments. It should beappreciated that various concepts introduced above and discussed ingreater detail below may be implemented in any of numerous ways, as thedisclosed concepts are not limited to any particular manner ofimplementation. Examples of specific implementations and applicationsare provided primarily for illustrative purposes.

FIG. 4 is a block diagram illustrating a control system 100 a formonitoring and controlling a dynamic environment, according to oneembodiment of the present invention. With reference again to FIG. 1, inwhich a conventional programmable logic controller (PLC) 50 is shown asmonitoring and controlling an automated process 10, in exemplaryimplementations discussed in greater detail below the control system ofFIG. 4 is configured as a replacement for the PLC 50 shown in FIG. 1.However, it should be appreciated that the control system of FIG. 4 isnot limited in this respect, and various control systems according toembodiments of the present invention, as well as constituent elementsthereof, may have wide applicability for monitoring and/or controlling avariety of dynamic environments, particularly those requiring lowlatency (i.e., significantly fast response time) and/or low variabilitylatency. One exemplary application of control systems according to thepresent invention is given by a dynamic environment in which machinevision techniques and/or equipment are employed, as discussed in greaterdetail below in connection with FIG. 10.

As illustrated in FIG. 4, the control system 100 a of this embodimentincludes a master processor 190 (also referred to as a “housekeepingCPU”) that is communicatively coupled to an action engine 110 a. Theaction engine 110 a may comprise one or more responsive co-processors(respectively indicated in FIG. 4 as co-processors 120 a-1 and 120 a-2;collectively indicated as co-processors 120 a). Each co-processor 120 aincludes an input interface 158 a and an output interface 160 a that arecoupled to co-processor logic (indicated respectively as controllers 130a-1 and 130 a-2; collectively controllers 130 a). Exemplary inputinterfaces 158 a output interfaces 160 a may include, but are notlimited to RS232 interfaces, Ethernet interfaces, universal serial bus(USB), and/or any other suitable parallel or serial communicationsinterfaces. Each co-processor controller 130 a is communicativelycoupled to a dedicated memory (indicated respectively as memory 140 a-1and 140 a-2; collectively memory 140 a) that stores one or moreconditions (indicated respectively as conditions 142 a-1 and 142 a-2;collectively conditions 142 a) and at least one predetermined action(indicated respectively as action 144 a-1 and 144 a-2; collectivelyactions 144 a) corresponding to the condition 142 a stored in the samememory 140 a. Although the action engine 110 a shown in FIG. 4 includesonly two co-processors 120 a, it should be appreciated that actionengines according to other embodiments are not limited in this respect,and may include only one co-processor or more than two co-processors.

In one aspect of the control system 100 a shown in FIG. 4, the controlsystem 100 a monitors, controls, and/or synchronizes a dynamicenvironment by using the action engine 110 a to evaluate conditions thatoccur on relatively fast time scales and by using the housekeeping CPU190 to evaluate conditions that occur on relatively slower time scales.More generally, as discussed above, in some embodiments the housekeepingCPU 190 essentially tasks the action engine with “paying attention” tomonitoring certain conditions of the dynamic environment during a timeperiod in which the housekeeping CPU 190 effectively is incapable ofdoing so itself. In one aspect, the time period during which the actionengine 110 a is particularly tasked with monitoring certain conditions(and taking action in response to same if necessary) is based at leastin part on a “response time” (also referred to as “latency”) of thehousekeeping CPU 190 (which response time results from limits placed onthe housekeeping CPU's ability to process information given the numberof different tasks or processes that the housekeeping CPU itself needsto attend to). In some examples discussed below, the time period duringwhich the housekeeping CPU delegates certain monitoring and controltasks to the action engine is based on a longest or worst-case responsetime of the housekeeping CPU that may be expected in the context of theparticular dynamic environment being controlled.

In view of the foregoing, in one exemplary implementation of the controlsystem shown in FIG. 4, the action engine 110 a screens forfast-occurring events by evaluating input signals 66 representing thedynamic environment against conditions 142 a that benefit from reflexiveresponses, i.e., responses executed faster than the latency of thehousekeeping CPU 190. Exemplary input signals 66 include, but are notlimited to: discrete inputs, such as digital values (bits), analogvalues, or digital representations of analog inputs; real-time versionsof discrete inputs; latched versions of discrete inputs; derivedversions of discrete inputs, such as counter values that are derivedfrom a pair of counters clocked in quadrature; and decoded contents ofmessages (e.g., packets) received from one or more communication ports.The input signals 66 may represent a single parameter (e.g.,temperature, pressure, position) constituting a condition of the dynamicenvironment or a collection of such parameters constituting a conditionof the dynamic environment.

To achieve this reflexive behavior, the controller 130 a of eachco-processor 120 a in the action engine 110 a compares the input signals110 a to a particular condition 142 a (or set of conditions 142 a).Unlike a general-purpose processor, each co-processor 120 a evaluatesonly the particular condition 142 a (or set of conditions 142 a) storedin its memory, which enables the co-processor 120 a to operate with low(and predictable) latency. If the controller 130 a determines that theinput signals 66 match the particular condition 142 a, the controller130 a executes the corresponding action 144 a. For example, execution ofa corresponding action 144 a may include transmitting one or more outputsignals 68 to other devices and/or systems. Alternatively, the action144 a may include forwarding an interrupt to the housekeeping CPU 190 toimplement the response.

At the same time, the housekeeping CPU 190 monitors the evolution of thedynamic environment through analysis of the input signals 66 and outputsignals 68. In certain circumstances (e.g., for slow evolutions of thedynamic environment), the housekeeping CPU 190 may respond directly toparticular input signals 66 by transmitting its own output signals. Inother circumstances, the housekeeping CPU 190 responds indirectly toevolutions of the dynamic environment by re-tasking the co-processors120 a, e.g., by updating and/or replacing some or all of the conditions142 a and/or (predetermined) actions 144 a stored in the memories 140 a.If the dynamic environment is an assembly line, for instance, thehousekeeping CPU 190 may re-task co-processors 120 a originallydedicated to tracking a first part to instead tracking a second partonce the first part has moved off the assembly line.

Dividing responsibility between the housekeeping CPU 190 and the actionengine 110 a allows the housekeeping CPU 190 to place the processingburden for the subset of events (e.g., fast-occurring events likely tooccur given a particular evolution of the dynamic environment)represented by conditions 142 a on the action engine 110 a. At the sametime, the housekeeping CPU 190 may continue to process conditionsassociated with slower evolutions of the dynamic environment. Thisdivide-and-conquer approach may reduce the overall latency and/or jitter(latency variation) of the system's response to events represented bythe input signals 66. In some cases, shifting the processing burden forfast-occurring events may also make the latency of the entire controlsystem 100 a substantially a function of co-processor latency.

Action Engines with Comparator Logic

FIG. 5 shows another illustrative action engine 110 b for monitoring,synchronizing, and/or controlling at least one aspect of a dynamicenvironment. Examples of such environments with which the system shownin FIG. 5, and particularly the action engine 110 b, may be employedinclude, but are not limited to, an assembly line, inspection line,autonomous or semi-autonomous vehicle (or vehicle convoy), powermanagement system (e.g., a smart grid), warehouse, industrial space,parking facility, airport, shipping port, surveillance system, amusementride, and/or communications network. For instance, the action engine 110b may be used for machine control and/or image triggering.

The action engine 110 b includes multiple co-processors (respectivelyindicated in FIG. 5 as co-processors 120 b-1 through 120 b-n;collectively indicated as co-processors 120 b). Each co-processor 120 bis a special-purpose computer processor that executes a limited numberof operations at high speed, i.e., speeds higher than can be achievedexecuting the same operations with a general-purpose computer or CPU,e.g., housekeeping CPU 190. Illustrative co-processors 120 b may beimplemented in FPGAs, ASICs, and/or any other suitable implementationknown in the art.

Each co-processor 120 b in the action engine 110 b includes a respectiveinput port (respectively indicated in FIG. 5 as input ports 158 b-1through 158 b-n; collectively indicated as input ports 158) coupled toan input bus 102 that is operably coupled to receive data from sensors,actuators, receive queues (e.g., Ethernet receive queues), and othersources of information about the dynamic environment. Although FIG. 5depicts n entries, those of skill in the art will readily appreciatethat exemplary action engines may have any number of co-processors 120b, e.g., 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024 co-processors120 b.

Each co-processor 120 b also includes a respective register(respectively indicated in FIG. 5 as registers 140 b-1 through 140 b-n;collectively indicated as registers 140 b) that stores representationsof one or more states or conditions (respectively conditions 142 b-1through 142 b-n; collectively conditions 142 b) and representations ofone or more actions (respectively actions 144 b-1 through 144 b-n;collectively conditions 144 b) to be executed by the co-processor 120 bas described below. Each condition 142 b may be independent of (andpossibly overlap with) the other conditions 142 b in the action enginesregisters 140 b. A condition 142 b may also be contingent uponsatisfaction of one or more other conditions 142 b in the action engine110 b—for example, they may be logically “ANDed” together into supersetsas described in greater detail below.

The registers 140 b can be implemented in any suitable type of memory,including but not limited to computer readable storage media such as avolatile or nonvolatile computer memory, flash memories, compact discs,optical discs, magnetic tapes, one or more floppy discs, circuitconfigurations in FPGAs or other semiconductor devices, or othernon-transitory media or tangible computer storage media. Each register140 b is dedicated to its respective co-processor 120 b; that is, theco-processors 120 b do not share memories. Dedicating a register 140 bto each co-processor helps reduce or eliminate contention issues.

Each co-processor 120 b also includes a comparator (respectivelycomparator 130 b-1 through 130 b-n; collectively comparators 130 b) orother logic element(s) that compare input signals 66 received via theinput bus 102 and input port 158 to the conditions 142 b. Because allthe co-processors 120 b have their own comparators 130 b and receive theinputs 101 simultaneously via the input bus 101, the co-processors 120 bcan compare the inputs 101 to their respective conditions 142 bsimultaneously. As a result, the number of co-processors 120 b in theaction engine 110 b does not affect the speed with which the comparisonsare performed.

If the input signals 66 match the conditions 142 b, the comparator 130 bemits an output (respectively outputs 132-1 through 132-n; collectively,outputs 132) indicative of the match. It is possible for one, more thanone, or none of the co-processors 120 b to include conditions 142 b thatmatch the input signals 66. Each co-processor 120 b may couple itsoutput 132 to an output bus 103 via an output port (respectively outputports 160 b-1 through 160 b-n; collectively output ports 160 b).

Each co-processor 120 b also executes the action 144 b stored in itsrespective register 140 b upon detection of inputs 101 that match itsrespective conditions 142 b. The action 144 b are coupled to a logicelement (respectively, logic elements 134-1 through 134-n; collectively,logic elements 134) controlled by the output 132 of the comparator 130b. When the logic element 134 receives an output 132 indicative of amatch between the inputs 101 and the conditions 142 b, the logic element134 executes the action represented by the action 144 b. In some cases,the logic element 134 may transmit additional information orinstructions, shown here as output signals 68, to other devices, such assensors, actuators, and other devices associated with the dynamicenvironment, via the output port 160 b and output bus 104. Illustrativeoutput signals 68 include, but are not limited to: discrete outputs,such as digital values, analog values, and/or digital representations ofanalog values; latched versions of discrete outputs; and/or output dataand machine operation commands encoded in message packages sent via oneor more communication ports (e.g., output port 160 b). In other cases,the action 144 b may be a “no-op” instructions in which the co-processor120 b does not perform any action.

The action engine 110 b is also coupled to a housekeeping CPU 190 viathe input bus 102, output bus 104, and additional connections to theregisters 140 b. (In other embodiments, one or more registers 140 b inthe action engine 110 b may be operably coupled to the housekeeping CPU190 via input ports 158 and input bus 102.) The housekeeping CPU 190performs general housekeeping task and loads and maintains theconditions 142 b and/or action 144 b in the co-processor registers 140b. For example, the housekeeping CPU 190 may replace or updatecondition/action pairs in one or more co-processors 120 b in response tothe action engine's identification of a particular state of the dynamicenvironment, indications that op-codes are out of date, instructionsfrom the action engine, instructions from users and/or other devices,etc. Since the action engine 110 b can respond “directly” to inputs fromthe dynamic environment without necessarily requiring resources from thehousekeeping CPU 190, the housekeeping CPU 190 therefore remainssubstantially free of any processing burden in connection withresponding to successive input states (i.e., the housekeeping CPU 190remains substantially “unloaded”); accordingly, the housekeeping CPU 190is available when needed to perform tests and actions that may not bepossible or practical for the action engine 110 b to perform itself. Inaddition, the housekeeping CPU 190 is not in a critical path forresponding to evolutions of the dynamic environment, so it does notdelay the action engine's response.

Action Engines with Event Tables and Scanners

FIG. 6 shows a system configuration of various components, including anillustrative action engine 110 c for monitoring, synchronizing, and/orcontrolling at least one aspect of a dynamic environment. Examples ofsuch environments with which the system shown in FIG. 6, andparticularly the action engine 110 c, may be employed include, but arenot limited to, an assembly line, inspection line, autonomous orsemi-autonomous vehicle (or vehicle convoy), power management system(e.g., a smart grid), warehouse, industrial space, parking facility,airport, shipping port, surveillance system, amusement ride, and/orcommunications network. For instance, the action engine 110 c may beused for machine control and/or image triggering.

The action engine 110 c includes an event table 112, which in turnincludes event table registers (collectively, event table registers 140c; respectively registers 140 c-1 through 140 c-5), each of which storesa representation of one or more conditions (collectively indicated inFIG. 6 as conditions 142 c; respectively indicated in FIG. 8 asconditions 142 c-1 through 142 c-5). Each event table register 140 calso stores a representation of one or more actions corresponding to thecondition(s) stored in the register 140 c (collectively indicated inFIG. 6 as instructions 144 c; respectively indicated in FIG. 8 asinstructions 144 c-1 through 144 c-5). The event table 112 and eventtable registers 140 c can be implemented in any suitable type of memory,including but not limited to computer readable storage media such as avolatile or nonvolatile computer memory, flash memories, compact discs,optical discs, magnetic tapes, one or more floppy discs, circuitconfigurations in field programmable gate arrays or other semiconductordevices, or other non-transitory media or tangible computer storagemedia.

Each event table register 140 c stores an independent condition 142 c.Taken together, the event table registers 140 c can store conditions 142c representing every possible state of the dynamic environment that canbe measured by one or sensors 40 coupled to the input bus 110. In manycases, however, the event table registers 140 c may hold areprogrammable subset of conditions 142 c, e.g., only those conditions142 c that benefit from actions 144 c executed more quickly than thelatency of the housekeeping CPU 190. In some cases, the conditions 142 cmay overlap; for instance, condition 142 c-1 may include temperature andpressure thresholds, and condition 142 c-2 may include temperature andposition thresholds. Although FIG. 6 shows only five event tableregisters 140 c for purposes of illustration, it should be appreciatedthat, in other embodiments, an event table 112 may have more or fewerregisters 140 c, e.g., tens, hundreds, or even thousands of entries. Ingeneral, virtually any number of conditions 142 c germane to aparticular environment, pursuant to which some response/reaction may berequired, may be represented in an event table 112 as an event tableregister 140 c.

In addition to representations of conditions 142 c, each event tableregister 140 c also includes representations of one or more actions 144c to be carried out if the state input matches the condition(s) 144 c.Accordingly, if a scanner 130 c of the action engine 110 c determinesthat the input signals 66 match a given condition 142 c stored in anevent table register 140 c, the scanner 130 c accesses the correspondingaction(s) 144 c stored in the event table register 140 c, and executesthe action(s) 144 c so as to control one or more aspects of the dynamicenvironment. To this end, the action engine 110 c also includes an inputport 158 c, an output port 160 c, and/or one or more other communicationinterfaces (e.g., input/output buses, Ethernet ports) to communicateinstructions accessed in the event table to one or more externaldevices, as well as receive the state input, as well as otherinformation relevant to the dynamic environment, from one or moresources of such information.

As shown in FIG. 6, the action engine 110 c further comprises a scanner130 c. The input port 158 c that provides a connection from the eventtable 112 and scanner 130 c to an input bus 102. FIG. 6 also illustratesthat the input bus 102 of the action engine 110 c is coupled to avariety of external devices, including (but not limited to) a CPU 190,as well as a semaphore register 150, a counter 42, one or more sensors40, and a communications interface in the form of a receive queue 44(e.g., an Ethernet receive queue). The scanner 130 c, which is alsoconnected to the input bus 102, includes digital logic (not shown inFIG. 6) that compares the set of conditions 142 c in each event tableregister 140 c to input signals 66 coupled to the input bus 102 from thehousekeeping CPU 190, the counter 42, the sensor(s) 40, the receivequeue 44, and/or any other suitable data source. In some cases, theinput signals 66 may include data derived from the dynamic environmentby one or more embedded application systems, such as a processor thatevaluates image data from a camera, position information from a roboticcontroller, and/or flow information from a mixer or flow control systemin a continuous process chemical reactor. In some implementations,pre-conditioning or pre-processing raw data may reduce the number ofbits required to represent the data, which in turn makes it possible toreduce the size of the registers 140 c.

FIG. 7 is a block diagram that shows one possible embodiment of thescanner 130 c in greater detail. The scanner 130 c includes comparatorlogic 131 that is coupled to action logic 132, sequencing logic 133, andone or more flag registers 135. Input signals 66, including but notlimited to counter 42 value(s), sensor 40 value(s), state change inputs,and flag states, are evaluated by the comparator logic 131 with respectto the data representing conditions 142 c from the event table 112 todetermine if the conditions 142 c are met. This “condition met” statusis passed to the action logic 132.

Referring again to FIG. 7, the scanner 130 c also includes action logic132 that receives the “condition met” status from the comparator logic131 along with data representing instructions 144 c from the event table112. The action logic 132 is also coupled to one or more flag registers135, semaphore registers 150 (FIG. 6), output registers 136,communication logic (not shown), counters, and data input circuitry.Depending on the state of the “condition met” status and the datarepresenting instructions 144 c, the action logic 132 may performoperations affecting the state of the flag registers 135, semaphoreregisters 150, output registers 136 coupled to an output port 160 b,communication logic 34, counters, and data input circuitry, asdelineated in more detail below. In addition, the action logic 132 iscoupled to event table write arbitration logic 134, which facilitatesthe changing of conditions 142 c and/or instructions 144 c in the eventtable 112, when, for example, an action has been executed and furtherevaluations of the condition/action pair are to be inhibited.

The sequencing logic 133 in the scanner 130 c (FIG. 7) synchronizes theactivities of the comparator logic 131, the action logic 132, and theevent table 112 (FIG. 6). It provides the read address to the eventtable 112, which determines which register 140 c in the event table 112is to be evaluated. The sequencing logic 133 also provides the writeaddress to the event table write arbitration logic 134 when the actionengine 110 c determines that conditions 142 c and/or instructions 144 cin the event table 112 are to be modified. The event table writearbitration logic 134 receives inputs from the housekeeping CPU 190 aswell as from other logic within the scanner 130 c to govern writeactivity to the event table 112. When contention arises between writeoperations from the CPU 190 and write operations from other logic withinthe scanner 130 c, priority may be given to the logic within the scanner130 c so that the scanner operation can continue uninterrupted. In thiscase of contention, a wait signal is asserted to the housekeeping CPU190 so that the CPU write operation is suspended until the event tablewrite arbitration logic 134 determines that the event table 112 isavailable to accept the write data from the CPU 190. In one embodimentof the scanner 130 c, the sequencing logic 133 causes a newcondition/action pair to be evaluated on every cycle of the master clock(not shown).

In various aspects, the scanner 130 c and event table 112 may beimplemented in a single co-processor, e.g., in an FPGA using a workinghardware description language (HDL) code. The scanner 130 c may also beimplemented as a unitary digital logic structure coupled to the one ormore storage media in which the event table is stored. Alternatively,the scanner 130 c may be implemented as multiple distributed logiccomponents communicatively coupled to the event table. For example, inone embodiment, the scanner 130 c may be implemented as multiple digitallogic components respectively dedicated to one event table register 140c, such that there is a one-to-one correspondence between an event tableentry and dedicated digital logic to compare input signals to one ormore conditions in a given event table register and access one or morecorresponding instructions as appropriate. In yet other embodiments,digital logic components constituting a portion of the scanner may bededicated or assigned to particular groups of multiple event tableregisters. Accordingly, it should be appreciated that the scanner of theaction engine, and the digital logic circuits constituting the scanner,may be implemented in any of numerous ways according to variousembodiments of the present invention.

In one exemplary implementation, the scanner of the action enginecompares the state input substantially simultaneously (e.g., inparallel) to multiple sets of conditions in the event table so thatappropriate instructions for responding/reacting to the state input maybe accessed (and in turn communicated to one or more external devices)with appreciably high speeds. As a result, the action engine exhibits asignificantly low latency with respect to processing informationrelating to respective states of the dynamic environment and takingactions in response to same.

For instance, the scanner 130 c may be implemented as a state machinethat processes a single register 140 c every two clock cycles. Duringthe first clock cycle, the scanner 130 c reads the condition 142 c. Thescanner 130 c performs the corresponding action 144 c during the secondclock cycle if the condition 142 c is met. The second clock cycle mayinvolve a write back to the action 144 c in the event table 112 toindicate that the appropriate operation has been completed for the nextscan. Implementations that involve especially complex conditions and/ora large number of input states may use more than two clock cycles toprocess a single register. In scanners 130 c that use multi-cycleexecutions, a dual ported memory having concurrent read and write cyclescan be implemented, where the write cycle writes back the register 140 cprocessed during a previous read cycle. State machine pipeline registers(as described below) in conjunction with the concurrent read and writecycles of the dual port memory will allow a new register to be processedevery cycle, significantly reducing latency.

Referring again to FIG. 6, it should be appreciated that a set of one ormore input signals 66, provided on the input bus 102 of the actionengine 110 c, may be obtained from a variety of sources coupled to theinput bus 102 (e.g., the housekeeping CPU 190, the counter(s) 42, thesensor(s) 40, etc.) and may be provided by a single source at a giventime or multiple sources at a given time. Such a set of one or moreinput signals 66 may, at least in part, represent the dynamicenvironment at a given point in time, and these input signals 66 may becompared (e.g., by the scanner 130 c) to each of the sets of conditions142 c stored in respective event table registers 140 c.

The input signals 66 are evaluated constantly to detect a change ofstate (rising or falling edge). At the beginning of each scan of theevent table 112, any input state changes discovered during the previousscan are presented as latched inputs (not shown) to the scanner logic.This means that any signals that pass through the input filters will bedetected, no matter how short their duration. Hence any change of statefor any input signal can be presented to the scanner logic, even iftheir duration of the state change is shorter than the duration of ascan.

In one exemplary implementation of the action engine 110 c shown in FIG.6, if the set of input signals 66 provided on the input bus 102 matchesthe condition(s) 142 c for a particular event table register 140 c, thescanner 130 c executes the corresponding action 144 c from that eventtable register 140 c. In some cases, these actions 144 c may includeacquiring or releasing a semaphore, or setting or clearing a flagcoupled to the scanner 130 c, which uses the semaphore or flag toevaluate conditions 142 c as described in greater detail below. Thescanner 130 c in turn transmits output signals 68 corresponding to amatched set of conditions to the dynamic environment, the housekeepingCPU 190, and a transmit queue 34 (e.g., an Ethernet transmit queue) viaan output bus 104.

Alternatively, or in addition, the scanner 130 c may be operably coupledto various peripherals. For example, the scanner 130 c may reset orlatch counters, latch input registers, set or clear output registers, orload entries into the transmit queue 34. In the case of multiplescanners, various ways of handling contention may be employed. Forinstance, reset/latch/set/clear input contention can be handled by ORgates. The transmit queue 34 may be dedicated to the scanner 130 c andhave its own circuit process for managing data. The scanner 130 c mayalternatively share the transmit queue 34 (possibly with other scanners130 c), and the circuit process may manage ownership of the queue 34.

In some cases, the actions 144 c are executed to one or more devicesexternal to the action engine 110 c (e.g., via one or more communicationinterfaces of the action engine) as a data packet (e.g., as employed invarious packet-mode computer networks, such as TCP/IP packets). Inimplementations in which data packets are employed to transmitinstructions relating to actions 144 c, in some embodiments the contentsof such packets may include not only the instructions themselves, butadditional data (e.g., metadata) that relates in some manner to theinstructions, the set of conditions corresponding to the instructions,and/or one or more other aspects of the dynamic environment. Theadditional data may include, but is not limited to, address information(e.g., an Ethernet media access control (MAC) address header) and/orpayload buffers, which may be filled in by the housekeeping CPU 190 in alocation referenced by an index stored in the event table register 140c.

In some implementations, the action engine 110 c selects or generatessuch data for inclusion in a packet payload (e.g., based on monitoringvarious information sources coupled to the input bus 102, and/or basedon various information that may be stored in memory in addition to theevent table 112). For example, when a given condition 142 c issatisfied, the scanner 130 c may select a corresponding payload bufferbased on an index stored in the corresponding register 140 c, then copycorresponding payload buffer to the transmit queue 34. In other cases,the data may include the number of a part being tracked through anassembly or inspection line. Alternatively, the data may includeinformation about one or more data sources (e.g., the location and/ororientation of a camera serving as a sensor 40 and providing imageinformation for evaluation) and/or the data may be associated withand/or represent some aspect of the state input itself (that is comparedto sets of conditions stored in the event table).

Master Processor (“Housekeeping CPU”)—Programming and Operation

In embodiments of a system configuration employing the action engine 110c and various other components, such as shown in FIG. 6, thehousekeeping CPU 190 loads and maintains the conditions 142 c andinstructions 144 c in the event table 112. In some cases, thehousekeeping CPU 190 may replace some or all of the conditions 142 c andthe instructions 144 c in the event table 112 in response to anevolution of the dynamic environment (i.e., changing conditions as afunction of time). Since the action engine 110 c can respond “directly”(e.g., autonomously, without intervention of the CPU 190) to inputsignals representing conditions of the dynamic environment withoutnecessarily requiring resources from the housekeeping CPU 190 (e.g.,during time periods in which the action engine is commissioned toevaluate particular conditions), the housekeeping CPU 190 thereforeremains substantially free of any processing burden in connection withevaluating these particular conditions; accordingly, the housekeepingCPU 190 is available to attend to other processes (e.g., perform testsand actions that may not be possible or practical for the action engine110 c to perform itself).

With respect to commissioning the action engine 110 c to evaluateparticular conditions during a given time period (or more generally,tasking one or more co-processors with evaluating one or moreconditions), in one embodiment the housekeeping CPU 190 is configured toallocate tasks to co-processors by segregating application-specificmachine coordination algorithms into distinct (e.g., orthogonal)procedural steps distinguished by their being conditional on the passageof time (e.g., either a known period of time, or an unknown period oftime that may occur given its being conditional on a collection offuture external inputs or a particular sequence of monitoredconditions). To this end, and with reference again to FIG. 6, thehousekeeping CPU or master processor 190 includes one or morecommunication interfaces 192 and/or one or more input/output (I/O) portsfor receiving input signals 66 representing conditions of the dynamicenvironment (as a function of time), as well as one or more processingunits 194 and memory 196 to store processor-executable instructions, andvarious program data as necessary, for the processing unit(s) 194 toimplement orthogonal procedural steps for controlling an action engine(or more generally one or more co-processors according to variousembodiments).

Procedural steps as disclosed herein can be executed independently ofeach other (e.g., by the processing unit(s) 194 of the master processor190) completely in parallel and in any order as their conditions are met(e.g., particular conditions are evaluated by either the masterprocessor 190 or the action engine 110 c to initiate a given proceduralstep). Each procedural step may include one or more of the following: 1)starting one or more processes, or instances of one or more processes;2) stopping one or more processes, or instances of one or moreprocesses; 3) performing one or more mathematical transformations; 4)presenting one or more outputs; 5) transmitting one or more messages,e.g., between the housekeeping processor 190 and one or more actionengines 110 c, between action engines 110 c, to devices in the dynamicenvironment, and any other specified destinations; 6) acquiring orreleasing binary semaphores to allow multiple processes to guaranteemutual exclusion from desired sections of program code; 7) latching thestate of peripherals, such as the inputs and counters; and 8) setting orclearing “flag” variables for inter-process synchronization andcommunication. (Flag variables may be Boolean variables that areimplemented by register peripherals that the event-table scanners haveaccess to as opposed to variables stored in the master processor'smemory.)

In one embodiment of the present invention, computer-implementableinstructions (e.g., written in the SCORE™ programming language) encodedon non-volatile, non-transitory computer-readable media accessible bythe master processor 190 describe machine coordination tasks specific toeach real world application (e.g., generation of output signals from oneor more co-processors/an action engine to ultimately control variousequipment in the dynamic environment). These instructions cause themaster processor 190 to implement one or more processes, or statemachines, possibly using one or more action engines 110 c and/or one ormore co-processors. Each process may also be implemented multiple timesby the same system, either in parallel, in sequence, or both.Concurrently executed copies of a given process are known as “instances”of the process, with each instance executed by a different slot 140 orset of slots in the action engine 110 c or different co-processor.

Each process can be considered as a state machine, with each state inthe state machine corresponding to a particular condition of the dynamicenvironment. The processes (state machines) include one-shot processes,which are executed once, and continuous processes, which are performed(e.g., repetitively) without interruption. Both one-shot and continuousprocesses may be halted or terminated before finishing, e.g., inresponse to a command from the master processor 190 or other source orupon reaching a predetermined point in the sequence ofcomputer-implementable instructions.

Each state machine includes one or more states, each of which may beimplemented as a “wait” statement, executed by an actionengine/co-processor, during which the action engine/co-processormonitors the dynamic environment for the occurrence of the particularcondition. In one significant aspect, the computer-implementableinstructions include a particular definition of a “wait” statement,having as arguments one or more conditions of the dynamic environmentthat, when satisfied, trigger execution of one or more actions and anotification of the master processor that the condition has been met.The “wait” statement essentially specifies that one or more actions willbe executed when one or more real world conditions are met. Thehousekeeping processor 190 may off-load wait statement conditions andassociated actions that are compatible with the action engine'soperations to the action engine. Pursuant to the programming languageonce compiled to be executed by the processing unit(s) 194 and themaster processor 190, blocks of instructions between wait statements areexecuted by the action engine/co-processor and/or the master processor190 until the next wait statement. For example, an action engine mayexecute one or more actions directly following a wait statement providedthat those actions are compatible with the action opcodes of theco-processor.

In at least one implementation, a wait statement causes the progress ofa process to pause until the condition clause is satisfied. This enablesthe master processor 190 to schedule processes by querying the currentwait statement condition of each process and continuing a process whenits condition is satisfied. Wait statements can have the format “waitfor <Boolean-expression>,” where <Boolean-expression> represents acondition of the dynamic environment. Subroutine calls may be made asdesired to evaluate the condition of the statement. For instance, thecondition may involve evaluation of a Boolean counter condition. Countervariables can accessed by name, optionally preceding the counter namewith the keyword counter. Counter comparisons can be made from aninitial value, such as a belt position when a part detect signal isgenerated. Automatically declared counter time can also be used tocompare durations precisely (e.g., with microsecond precision). Someexamples include (hash marks “#” indicate comments):

wait for total > 2; wait for canContinue( ); # the subroutinecanContinue returns a Boolean wait for computeTotal( ) > 99 wait forcounter position >= 100 from detectLocation wait for time >= 100us fromdetectTime; # includes “from” keyword wait for flagA and flagB orbooleanCThe “from” keyword removes the need for the developer to worry aboutcounter roll-over for applications where a counter reset is notdesirable.

A wait statement may also be used to wait for a particular time periodto elapse by using the argument <duration-expression>: “wait for<duration-expression>.” This time period may be expressed as an absolutevalue, such as a time in milliseconds; a relative period, such as a timeperiod required by another process; or a time expressed as a variable.If the expression involves calling subroutines or evaluating variablevalues, those variable values are evaluated only when the wait statementis processed the first time. Some examples include:

wait for 1ms; wait for pauseDuration; # where the variable is typetimespan wait for computeWaitTime( ); # will call the subroutine once

A wait statement may also be used to wait for a rising or falling edgeof a particular input: “wait for <edge> of input <input>.” The inputgiven can be either the input index or the named input which would bepreviously declared. Multiple inputs can be given with an edge on anyone of them satisfying the condition. Named and indexed inputs can bemixed in the OR'd list of inputs. Multiple inputs can be separated byeither the OR keyword or a comma. Input indexes start at 0. Someexamples include:

wait for rising edge of input 0 wait for falling edge of inputsPartDetect, DisableSwitch wait for rising edge of input 1,2,3 or 4 orDisableSwitch

A wait statement may also be used to wait for one or more inputs tochange to a desired state (e.g., a set state or a cleared state): “waitfor <state> input(s)<input-list>.” The “AND” keyword may be used toindicate all inputs are required to be in the desired state to satisfythe condition. Similarly, the “OR” keyword may indicate that thecondition is satisfied if any of the inputs reaches the desired state.Some examples include:

wait for set input 3 wait for set input 3, 12 and Enable wait for setinputs 3 and 12 and Enable wait for clear inputs inProgress or Abort

A wait statement can be used to wait for one or more flags to be set orcleared: “wait for <state> flag(s)<flag-list>.” This is analogous towaiting one or more inputs to be set or cleared as above. Multiple flagscan be given and the “flag” keyword can be used in the plural form forreadability. Flags are indicated by a declared flag variable. Someexamples include:

wait for set flag goAhead; wait for set flags doneA, doneB and doneCwait for set flag finished set or finished clear wait for cleared flagavailable[i]

A wait statement can be used to wait for one or more trigger ladder tofire: “wait for trigger ladder <integer-expression>.” A trigger laddermay be specified by its index, with trigger ladder indexes starting at0. Examples include:

wait for trigger ladder 1 wait for trigger ladders 1 or 3 wait fortrigger ladders 0, 1, 2 or 3

Other types of wait statements include, but are not limited to:

-   -   Waiting for a quadrature encoder counter to decrease: “wait for        decreasing counter <counter>.” This may be used with another        condition, such as a rising edge of a part detection input;    -   Waiting a for quadrature encoder counter to increase: “wait for        increasing counter <counter>”. This may also be used with        another condition, such as a rising edge of a part detection        input;    -   Waiting for a previous send statement in the same process to        complete transmission “wait for send (sender) to finish”. For        example, it may be used to wait for an Ethernet SureSync™ event        transmission to finish before the process modifies the payload        so as to avoid corrupting the payload for the transmission in        progress;    -   Waiting for messages to arrive at an event packet receiver ports        in the co-processor or action engine: “wait for message.” The        device IDs of the sending devices may be either stored in the        power on configuration or configured at runtime by a host        computer. If the event sender is relevant, the wait statement        can be followed by an “if-else if” statement that switches on        the message port value. In certain embodiments, a process that        waits for a message will not wait for anything else. This        enables the process to either run continuously or wait for a        message, which in turn enables the scheduler to give a received        message to the process. If the scheduler reads a message from a        receiver peripheral and there is no process waiting for a        message, however, the message may be discarded.

Multiple conditions can be combined together so that all must besatisfied at the same time before the wait statement is completed. Thiscan done by combining the “for” clauses in the wait statement with the“AND” keyword. Examples include:

wait for set flag goAhead and for set input Enabled; wait for set inputEnabled and for counter ticker > 100;In some instances, the action engine/co-processor may not execute a waitstatement until all outstanding message sends have been completed. Forcommunication with a 1×1 device, which may have a high latency inperforming a message acknowledgement/no acknowledgement handshake, thiscan result in delays of over a millisecond. If this is not desirable, aseparate one-shot process may be used to send the message, removing thislatency from the main process.

In general, the master processor 190 delegates as many conditions aspossible to the action engine(s) 110 c and/or co-processors. Typically,the master processor 190 assigns one condition to each slot 140 in theevent table 112 of the action engine 110 c and/or to each co-processor.It may assign the conditions to the respective slots 140 and/orco-processors based on the initial compiling of the instructions, adesired latency, the capabilities of the action engine 110 c and theco-processors, the conditions themselves, and/or its own capabilities.For instance, the master processor 190 may determine a first subset ofconditions for evaluation by a particular co-processor based on at leastone of: a time period in which the first subset of the plurality ofconditions is expected to occur in the dynamic environment; a particularsequence in which the plurality of conditions is expected to occur inthe dynamic environment; at least one previous action taken in thedynamic environment; a present state of the dynamic environment; aresponse time of the master processor; and at least one attribute of theat least one co-processor (e.g., functioning status, processing speed,memory size, input signal number, input signal type, output signalnumber, and output signal type). In some examples, the co-processor isconfigured to evaluate a number of conditions that is smaller than somefixed maximum number of conditions, which may be based at least in parton a maximum permissible latency defined by a required response time inthe dynamic environment

The master processor may also re-assign conditions dynamically, e.g., inresponse to the evolution of the dynamic environment, new instructions,and/or previously stored instructions. By delegating conditions to theaction engine(s) 110 c and/or co-processors, the master processor 190can perform other processing tasks instead of monitoring the conditionsin a serial fashion. For example, the master processor may configure agiven co-processor at a first time to evaluate only first subset ofconditions and to provide control information representing the firstaction in a plurality of actions if the first subset of conditions issatisfied. Later, at a second time, the master processor reconfiguresthe co-processor to evaluate only a second subset of conditions and toprovide additional control information representing another action ifthe second subset is of conditions is satisfied. In some cases, themaster processor may determine the second subset of conditions based atleast in part on whether or not the first subset of conditions issatisfied. In at least one of these cases, the master processordetermines the second subset of conditions based on at least one of: atime period in which the second subset of conditions is expected tooccur in the dynamic environment; a particular sequence in which theconditions is expected to occur in the dynamic environment; a presentstate of the dynamic environment; at least one previous action taken inthe dynamic environment; and the master processor's response time. Themaster processor may determine the second subset of conditions based onat least one of the co-processor's attributes, which include but are notlimited to: the co-processor's functioning status (e.g., idle, active,etc.); a first number of the input signal processed by the co-processor;a first type of the input signal processed by the co-processor; a secondnumber of the output signal processed by the co-processor; and a secondtype of the output signal processed by the co-processor.

In one aspect, the master processor 190 determines how to delegateconditions (and possibly actions as well) according to compiledcomputer-implementable instructions from an optimizing compiler (notshown). As understood by those of skill in the art, the compilertransforms the user-written source code (e.g., in the SCORE™ programminglanguage) into a target language, such as object code, that can beexecuted by the master processor, the action engine(s), and/or theco-processor(s). In performing this transformation, the compiler maycompile the source code in the order presented in the source code andproduce object code with similar or roughly analogous ordering.

The compiler may also analyze the state machine(s) generated bycompiling the source code, e.g., by going from state to state along theedges (actions) connecting the states (wait statements/conditions). Inone example, a user supplies the compiler with a profile of theavailable action engine(s) and/or co-processor(s), e.g., by providingcommand-line arguments to the compiler. The compiler uses this profileto designate certain conditions and certain actions in the compiledobject code as within the capabilities of the available action engine(s)and/or co-processor(s). The master processor may assign these conditions(and possibly the actions as well) to the action engines orco-processors designated in the compiled object code. In someembodiments, the compiler determines these allocations of actionengine/co-processor resources to designated conditions (and actions) atcompile time, and these allocations remain static.

In other embodiments, the master processor may allocate or re-allocateaction engine/co-processor resources to designated conditions (andactions) in a dynamic fashion, e.g., in response to the evolution of thedynamic environment or changes in system or component status. In such adynamic environment, the master processor may create and/or maintain aprofile of the available action engine/co-processor resources. Forinstance, the master processor may obtain information about theavailable action engine/co-processor resources by polling the operablycoupled action engine/co-processor device(s), by receiving statusupdates from the operably coupled device(s), and/or by receiving theprofile from a user via command-line arguments or any other suitableinterface.

The master processor 190 may also create and maintain a list ofprocesses (state machines), including the status (state(s)) of thosedelegated in whole or in part to the action engine(s) 110 c and thosethat it reserves for itself. During operation, the master processor 190uses this list to advance each of the state machines implemented by thesystem. For example, a given co-processor may be tasked with monitoringthe dynamic environment for a particular condition (e.g., the arrival ofa part at a designated point in an assembly line). The process thenenters a “wait” state during which it monitors the dynamic environmentfor the condition. When the co-processor determines that the conditionhas been met (e.g., the part arrives at designated point), the processexits the wait state to perform a predetermined action (e.g., itinstructs a camera to take a picture of the part). The co-processor alsonotifies the master processor 190 that its condition has been met bytransmitting a notification signal (“notification” for short) to themaster processor 190. For instance, the co-processor may generate amatch signal if a particular condition of the dynamic environmentmatches the condition monitored by the co-processor and provide thematch signal to the master processor as the notification signal.

Upon receiving a notification signal (match signal) from theco-processor that a condition has been met, the master processor 190advances those state machines waiting for the notification on its listof state machines, including the one implemented by the co-processor.Depending on the state machine, the master processor 190 may note thatthe condition has been met and allow the co-processor to continueimplementing the process, or it may halt the state machine (process)implemented by the co-processor and cause the co-processor to implementanother state machine. It may also use the notification to start, halt,or advance other state machines implemented by the system.

In sum, in some implementations, the wait statement condition evaluatedby the co-processor for a single processor may have severalsub-conditions combined with Boolean logic followed by one or moreprocedural steps to be taken on satisfaction of the condition as a wholeand/or sub-conditions; this is what the co-processor is commissioned todo for a single process instance at any given time. When the conditionis satisfied and the actions are completed, the co-processor notifiesthe master processor, which can re-commission the co-processor for thenext wait statement in the process.

Each state (condition) may have associated with it at least oneparticular action. If possible, the master processor 190 also delegatesthe action(s) associated with a particular condition to the same slot140 or co-processor assigned to monitor the particular condition. Insome embodiments, the master processor 190 delegates actions involvinginputs and outputs to the action engine 110 c and/or co-processors 140.These actions may include, but are not limited to: sending packets,setting outputs, clearing outputs, adding outputs, latching counters,setting flags, clearing flags, acquiring semaphores, releasingsemaphores, and no operations (no-ops). In some cases, the masterprocessor 190 delegates actions based on the capabilities of the slot140 or co-processor assigned to monitor the associated condition. It mayalso assign the condition to the slot 140 or co-processor based on theassociated action and the ability of the slot 140 or co-processor toperform the associate action.

The master processor 190 may also delegate a condition to a slot 140 orco-processor while reserving execution of the associated action toitself. For instance, the master processor 190 may execute all actionsrelated to accessing information in memory, including but not limitedto: storing information in memory; retrieving information from memory;incrementing variables in memory; and arithmetic involving numbersstored in memory. The master processor 190 may also execute other typesof actions as well on an as-needed or as-desired basis.

Below are several pseudo-code examples of processes (state machines) andsub-processes suitable for implementation using the systems and devicesdisclosed herein, including the system shown in FIG. 6. Hash marks (#)indicate comments in each example.

Example 1 Continuous One-State Process

continuous process send_on_edge with instances i := 0..7 begin wait forrising edge of input i # state (condition no. 1) send sender i # action(executed by co-processor) end

Example 1 is a continuous process, called “send_on_edge,” in which aco-processor is tasked with waiting for a rising edge (the condition) ofinput i and sending a packet (the action) to another device uponsatisfaction of the condition. The co-processor also notifies the masterprocessor that its condition has been met upon detecting the risingedge. In this example, once the co-processor has sent the packet, themaster processor reloads the same condition and action opcode pair inthe co-processor's memory. The co-processor continues to monitor therising edge of input i until the co-processor is halted or interrupted,e.g., by the master processor 190. This process is implemented eighttimes (i=0 . . . 7), with each instance running on a separate slot inthe action engine or on a corresponding co-processor.

Example 2 Continuous Two-State Process

continuous process send_on_pulse with instances i := 0..7 begin wait forrising edge of input i - # state no. 1 (condition no. 1) send sender i #action no. 1a (executed by co-processor) set output i+8 # action no. 1b(also executed by co-processor) wait for 100ms # state no. 2 (conditionno. 2) clear output i+8 # action no. 2 (executed by co-processor) end

Example 2 is a continuous process, called “send_on_pulse,” in which aco-processor alternates between two states depending on the evolution ofthe dynamic environment. In the first state, the co-processor waits fora rising edge to appear on input i as in Example 1 (this is the firstcondition of this process). Once the co-processor detects the input, itsends a packet to another device and notifies the master processor thatthe first condition has been met as above. It also performs anotheraction—it sets output i+8—before proceeding to its second state (“waitfor 100 ms”). In this second state, the co-processor waits foroccurrence of the second condition, elapsation of 100 ms. Once thiscondition is met (i.e., once 100 ms has elapsed), the co-processorperforms its second action—clearing output i+8—and notifies the masterprocessor that the second condition has been met. It then transitionsback to the first state to wait for the first condition to occur again.Like the process in Example 1, the Example 2 process continues until itis halted or interrupted, e.g., by the master processor 190. It is alsoimplemented eight times (i=0 . . . 7), which each instance running on aseparate pair of slots in the action engine or on a correspondingco-processor.

Example 2 is performed with at least two slots in the action enginebecause it involves two actions associated with one condition—both “sendsender i” (action no. 1a) and “set output i+8” (action no. 1b) aretriggered by satisfaction of “rising edge on input i” (condition no. 1).Condition no. 1 and action no. 1a are loaded into the first slot, andaction no. 1b is loaded into the second slot, which is chained to thefirst slot. The second slot is also loaded with the condition “doalways” which is implemented as “counter[0]>=0,” and which causes it toexecute whenever condition no. 1 is met (see below for a more detaileddiscussion of “chaining” slots together).

Example 3 Continuous Process with Master Processor Action

continuous process send_sequence with instances i := 0..7 begin staticunsigned integer sequence := 0 # declaration payload p; - # declarationp.dword[0] := sequence; # master processor action wait for rising edgeof input i # condition no. 1 send sender i with payload p - # action no.1a (co-processor) sequence++; # action no. 1b (master processor) waitfor sender to finish - # condition no. 2; action 2 is a no-op end

Example 3 is another continuous process, entitled “send_sequence,” inwhich a co-processor monitors conditions and the co-processor and themaster processor each execute actions in response to detection of theconditions. In this case, the process begins with the declaration of astatic variable named “sequence” (“static unsigned integer sequence”)and a 16-byte payload p that goes out with every event packet. Oncethese have been initialized, the master processor sets a word(“p.dword”) in the payload to the value of the “sequence” variable. Theco-processor then enters a wait state in which it monitors the dynamicenvironment for a rising edge on input i. When it detects the risingedge, it notifies the master processor that its condition has been metand sends the payload, which may trigger a camera or other device thatreceives the payload.

Upon receiving the notification that the condition has been met, themaster processor increments the variable “sequence.” The masterprocessor performs this action because incrementing a variable involvesaccessing information in memory, which is often beyond the capabilitiesof an action engine or a co-processor. The master processor alsoadvances the state machine to its next state, in which the co-processorwaits for the sender to finish its action. If the co-processor detectsfulfillment of this condition, it performs the corresponding action. Inthis case, the corresponding action is a “no operation,” or “no-op,” sothe code does not include a specific command. The co-processor alsonotifies the master processor that the condition has been met, and themaster processor advances the state machine to its next state (here,back to the “wait for rising edge of input i” state) in response to thenotification. Like the processes in Examples 1 and 2, the Example 3processes runs until it is halted or interrupted and is implemented ineight separate instances.

In example 3, condition no. 2 (“wait for sender to finish”) is intendedto prevent procedural statements from overwriting a payload buffer (p inExample 3) until the send is completed, which happens in anon-deterministic time period due to network contention and variance incommunication protocol latency. This is because the co-processor mightnot be able to get access to the desired physical network resource whena send action is used. There are several possible ways to deal withaccess issues, including but not limited to: (a) adding queues to storethe payloads and port numbers for storage before processing; (b) holdingthe notification to the master processor until the send has completed;and (c) adding another notification to the master processor that thesend has completed and notifying the master processor of the conditionsatisfaction and action completion immediately. Option (a) may not beoptimal in field-programmable gate array (FPGA) implementations due toFPGA resource restriction. Option (b) may introduce extra delay becausea send completion can take up to 1 ms due to slow handshaking speed inthe event message protocol with non-real time peers (e.g., hostcomputers running MS Windows®). Option (c) allows the master processorto run non-co-processor-compatible actions after a wait statementimmediately, but prevents the master processor from modifying theevent-table slots until the send has completed. In some implementations,each wait statement has an implicit “wait for send to finish” since theslots cannot be overwritten until all send statements ahead of the waitstatement have been completed.

In some cases, including the one illustrated in Example 4 below, themaster processor evaluates a “flow control statement,” such as an “if”statement, to determine how to advance the state machine. For instance,the evaluation may yield a first result that causes the master processorto advance one or more state machines to particular first states or asecond result that causes the master processor to advance one or morestate machines to particular second states. Flow control statements mayalso be used to decide to interrupt, pause, or halt on-going processesand to initiate other processes.

Example 4 Flow Control Statements

quadrature counter PartPosition on inputs 0, 1 # declaration wait forcounter partPosition >= rejectDistance from position # condition(co-processor) if votes < 2 OR input DoReject is set - # flow controlstatement set output reject # co-processor action failure_count++ #master processor action wait for counter time >= rejectDuration from now# condition (co-processor) clear output reject # co-processor actionelse wait for counter partPosition >= acceptDistance from position #condition (co-processor) set output accept # co-processor action waitfor acceptDuration # condition (co-processor) clear output accept #co-processor action endif

Example 4 is a sub-process that includes a flow control statement. Thesub-process of Example 4 includes four states, each of which isindicated by a “wait” statement and a particular condition of thereal-world environment, e.g., is the part position counter greater thanor equal to a predetermined value from a part's current position(“counter part Position>=rejectDistance from position”). As in Examples1-3, an action engine or co-processor evaluates each condition and, ifthe condition is met, notifies the master processor and performs anappropriate action, such as a no-op, clearing an output, or setting anoutput. The master processor advances the state machine and, optionally,acts in response to the notification.

In Example 4, the master processor controls the flow of the statemachine by evaluating a flow statement (“if votes<2 OR input DoReject isset”) relating to whether or not a part has passed inspection at twodifferent inspection stations. In another part of the overall process(not listed above), the inspection stations “vote” on the part'squality, and the master processor increments a variable “votes” inresponse to the inspection stations' outputs. At the same time, theco-processor monitors the part's position. If the co-processor sensesthat the part has reached a particular position, it notifies the masterprocessor, which evaluates the flow control statement in response to thenotification. If the master processor determines that the part hasfailed inspection (e.g., because the “votes” variable is less than 2 orthe “DoReject” input is set), the master processor increments a failurecount (“failure_count”) and causes or allows the co-processor to rejectthe part by setting the “reject” output. The state machine then advancesto a state in which the co-processor waits for the counter time to equalor exceed a specified time period (“rejectDuration”). If the part hasnot failed inspection, the master processor advances the state machineto a state in which the co-processor waits for the part position counterto equal or exceed another variable (“acceptDistance”).

Examples 3 and 4 also illustrate the use of declaration statements toset variables and to configure peripheral devices, e.g., cameras, etc.Declarations may be used to set variables stored in the masterprocessor's memory, like the “sequence” variable in Example 3 or the(implicitly) declared “rejectDistance” and “position” variables inExample 4. They can also set counter values, like the “part Position”counter in Example 4, which is declared to be a quadrature counter “partPosition” on inputs 0 and 1. It could also be declared to be a pulsecounter “part Position” on the rising edge of input 2.

Other declarations may set peripheral variables, including input andoutput variables. Inputs can be declared to have pulse filters. Outputscan be declared to have pulse widths and polarity inversions. Thecounter and other peripheral variable declarations get compiled intoinstructions executed by the master processor, which loads theconfiguration registers of the peripheral devices. When the counter isused in the program, the event table conditions and actions access thecounter allocated by the compiler.

Example 5 Setup Process

one-shot process setup begin for i := 0..7 do start processsend_on_sequence[i] done end

Example 5 is a set-up process that the master processor uses to task theaction engine/co-processors with different instances of a particularprocess. Unlike the processes in Examples 1-4, the Example 5 processdoes not involve any conditions. Instead, it is a simple one-shotprocess that creates eight instances of another process (here, the“send_on_sequence” process from Example 3). Each of these instances runson a corresponding slot in an action engine or on a separateco-processor.

In various embodiments, any language statement (computer-implementableinstruction) can be executed on the housekeeping CPU 190, but greater orsmaller sets of language statements can also be executed by one or moreaction engines described herein. Any statements that cannot be executedon the action engines of a particular embodiment of the invention may berun on the housekeeping CPU 190. In general any statements that can berun on the action engine of a particular embodiment will be allocated bythe housekeeping CPU 190 to the action engines. Statements or groups ofstatements may be cancelled at any time prior to their execution.

In one embodiment, the computer-implementable instructions permit thatany processes described in an appropriate computer language (e.g.,SCORE™) can be run simultaneously and that multiple instances of a givenprocess may also run concurrently. In one aspect, the language iscompiled into condition/action pairs described in greater detail above;in exemplary implementations, such condition/action pairs are assembledinto an event table which may be scanned at a high and fixed rate (e.g.,as discussed above in connection with the event table 112 and actionengine 110 c of FIG. 6). The condition/action pairs may also be chainedas described in greater detail below.

With reference to FIG. 6, in one embodiment the housekeeping CPU 190 mayadd and remove entries to the event table 112 of an action engine 110 cwithout affecting or interrupting the operation of the action engine 110c. If necessary due to the housekeeping CPU word size (which may be,e.g., 32 bits) being less than the width of the event table register 140c (which may be, e.g., 64 bits) a given register 140 c can be written inpart by writing the input conditions to zero first, then writing theaction second. Registers 140 c that are currently not in use may have azero first word which indicates a “not in use” conditional operationwhich can never be satisfied. The scanner 130 c will not consider anyevent table conditions 142 c in its scan that have a “not in use”condition, so instructions 144 c in a partially written event tableregister 140 c will not be executed before the housekeeping CPU 190finishes writing the partially written event table register 140 c.

In another aspect, any statement or chained group of registers 140 cthat the housekeeping CPU 190 may allocate to the action engine 110 cwill either run in their entirety, or not at all. In particular, bywriting chained groups into contiguous event table registers 140 c fromthe first to the last (with respect to the scan direction) with zeros,then the last to the first (again with respect to the scan direction)with the new conditions 142 c and actions 144 c, no condition/actionpairs will be processed (e.g., by the scanner 130 c of the action engine110 c) unless all are processed, even if the scanner 130 c passesthrough the addresses of the corresponding section of memory multipletimes while the housekeeping CPU 190 is writing the chained group; thescanner's rules are such that it will not execute the actions of anevent table register 140 c in a chained group, even if that event tableregister's own input conditions are met, unless all of the inputconditions of all of the preceding event table registers 140 c up to andincluding the next previous event table register 140 c whose chain bitis not set are also met. Since each new event table register 140 c isbeing written in a section of event table registers 140 c set to zero,the prior event table register 140 c will not have valid inputconditions and so neither it nor the event table register 140 c justwritten will be executed.

Similarly, by clearing a set of chained event table registers 140 c fromthe first to the last (e.g., by filling the registers 140 c with allzeros or all ones), and for each event table register 140 c beginning byclearing the input conditions for each event table register 140 c first,at a rate equal to or slower than the rate at which the scanner 130 c isaddressing the event table registers 140 c, the housekeeping CPU 190 mayreplace or clear even a chain of event table registers 140 c for aprocedural step that had been allocated to a particularco-processor/action engine in such a way that either the entire set ofchained registers 140 c will be executed, or none will be executed.

The foregoing techniques for programming the master processor 190,efficiently compiling the program language to provide executable code(e.g., for the processing unit(s) 194 and the master processor 190), andthe resulting procedure implemented by the master processor 190 forupdating an event table 112 of an action engine 110 c (or more generally“programming” one or more co-processors to evaluate particularconditions) yields several unique advantages. This methodology producesan extremely compact set of code that can run very rapidly on anygeneral-purpose processor (with or without one or more action engines orother co-processors). However, when employed in connection with theaction engine 110 c shown in FIG. 6, and in particular with the scanner130 c, these techniques yield completely deterministic operation evenwhen the evolution of conditions in the dynamic environment wouldrequire code execution to branch, and/or function calls to be madeand/or cancelled for conventional systems. In fact these transitions canbe made without rearranging memory pointers in the action engine 110 c,since the inventive techniques described above allow multiplesubroutines (e.g., chains of event table register 140 c) to run tocompletion without signaling back to the calling process (in the masterprocessor 190). The simplicity of the instruction set, which does nothave any loops or jumps, keeps the run time of the co-processor/actionengine program space deterministic.

Also note that the housekeeping CPU 190 does not need to be dedicated tohousekeeping for the action engine(s). Housekeeping could be done by aprocess and/or device driver on a general-purpose operating system suchas Linux or Windows. The action engine could be on a peripheral card(such as a PCI) along with the counters, digital and/or analog I/Ointerfaces, etc., allowing a general-purpose computer to achieve thesame precision in event handling as a special-purpose embedded computerwhen working in tandem with the action engine(s) described herein. Theaction engine and/or separate co-processors may also be implemented inone or more field-programmable gate arrays (FPGAs) or as a collection ofother suitable processors.

Pipelining, Latency, and Jitter

In one exemplary implementation of the action engine 110 c shown in FIG.6, the scanner 130 c is configured to implement a “pipelining” techniqueto make comparisons of the input signals 66 to the conditions 142 c. Asunderstood by those of skill in the art, “pipelining” is a computationaltechnique that increases throughput by splitting a computation into aseries of stages that are connected to form a computational “pipe.” Eachstage of the pipe performs its part of the computation (e.g., thecomparison of the input signals 66 to the set of conditions 142 c) inparallel with the other stages, much like a worker on an assembly line.Pipelining accelerates the action of the scanner 130 c such thatregardless of how long it may take to compare the input signals 66 to agiven condition 142 c, the time spent on each register 140 c is limitedto one clock cycle.

With respect to calculating a “latency” of the action engine, i.e., thetime period required to compare a particular input state of the dynamicenvironment at a given time to the multiple sets of conditions containedin the event table and transmit one or more instructions in response tothe input state, in some exemplary embodiments such a latency may bederived in consideration of a pipelining technique implemented by theaction engine 110 c. For example, the time it takes for the actionengine 110 c to compare the input signals 66 and/or discovered statechanges (see paragraph 89 above) to a particular set of conditions 142 cand transmit one or more instructions in response equals the time ittakes the scanner 130 c to reach the corresponding event table register140 c plus the propagation time through the pipeline, which depends onthe number of stages in the pipeline. For an event table 112 with 128registers 140 c and a scanner 130 c clocked at 100 MHz with athree-stage pipeline, the longest possible time from input to output is1.31 μs, which corresponds to a condition 142 c that occurs at the verybeginning of a scan through the event table 112 but is not used untilthe very end of the scan through the event table 112 plus a 0.03 μspropagation time through the pipeline (i.e., three clock cycles). Theshortest possible time from input to output is 0.030 μs. Thus, theaction engine 110 c compares the input signals 66 and/or discoveredstate changes to the sets of conditions 142 c with a latency, or timedelay, that is bounded by the number of registers 140 c in the eventtable 112, the number of stages in the pipeline, and the clockfrequency.

An additional advantage of using an event table register 140 c toevaluate a small number of conditions 142 c very quickly is that thevariation in latency is very low. Jitter can be defined as thedifference between the longest latency and shortest latency. For anevent table register 140 c that evaluates a single condition 142 c, thevariation in latency is minimal, and may even border on zero dependingon how incoming and outgoing data is transmitted. In the example above,the longest possible latency is 1.31 μs, and the shortest possiblelatency is about 0.03 μs, which corresponds to a jitter of 1.28 μs, orone scan time. (Applying input filters, discovering input state changes,or receiving and transmitting data via Ethernet packets may introducevariable delay independent of the action engine 110 c.)

Low jitter is especially useful in applications—e.g., triggeringimages—in which long response delays are perfectly acceptable so long asthe latency is very repeatable, and in which even much shorter maximumlatencies are not acceptable if the individual latencies were highlyvariable. In machine vision applications, for instance, reducing thejitter makes it possible to reduce the sensor field of view, which inturn allows for higher resolution images of the scene of interest.Consider a situation in which the time window for imaging a fast-movingpart is about 10 μs, but the jitter is much larger than 100 μs as itwould be with a PLC. Capturing an image of the part requires expandingthe time window to substantially greater than 110 μs by increasing thefield of view to be well over eleven times the size of the part itself,which in turn reduces the number of pixels on the sensor dedicated toimaging the part by a factor of more than eleven. In contrast, an actionengine 110 c with a jitter of about 2.5 μs can be used to acquire animage of the same part with about 80% of the sensor's active areadedicated to imaging the part itself.

Condition/Action Pair Memory Structures and Execution

Embodiments of the present invention may include particular memorystructures to store the one or more “condition/action pairs.” In theaction engine 110 c shown in FIG. 6, for example, the event table 112provides dedicated memory in the form of multiple registers 140 c,respective ones of which store a condition/action pair as a particularsequence of bits (represented generally in FIG. 6 by a condition 142 cand an action or “instruction” 144 c). Alternatively, one or moreregisters 140 c may include multiple adjacent memory registers, arrangedas a first number of bits representing the condition to be evaluated,and a second number of bits representing an action to be taken if thecondition is satisfied. Generally speaking, various embodiments, such asthose shown in FIGS. 5 and 6, may include memory structures in the formof one or more registers (e.g., registers 140 b in FIG. 5; registers 140c in FIG. 6) that hold respective condition/action pairs as somearrangement of bits in a given register.

It should be appreciated that, in some instances, a given actioncorresponding to a particular condition that is satisfied may be to takeno action relating to control of one or more devices in the dynamicenvironment. Stated differently, one possible action for a givencondition/action pair is to take no affirmative action in the dynamicenvironment, also referred to herein as a “no-op.” In some instances ofa no-op, as discussed in greater detail below, the action engine maynonetheless notify the master processor if the particular conditionbeing evaluated is satisfied, and/or move on to evaluation of one ormore other conditions as specified in subsequent registers of the eventtable.

It should also be appreciated that the concept of a “condition/actionpair” may be implemented in diverse manners according to variousembodiments disclosed herein. For example, in some implementations, thecontents of memory representing the condition portion of a particularcondition/action pair may include some number of adjacent bits within agiven register, and/or may include some number of bits dispersed in thegiven register with intervening register contents not necessarilypertaining to the condition portion. Similarly, the contents of memoryrepresenting the action portion of a particular condition/action pairmay include some number of adjacent bits within a given register, and/ormay include some number of bits dispersed in the given register withintervening register contents not necessarily pertaining to the actionportion. Accordingly, a wide variety of content organization within agiven memory location/register representing a given condition/actionpair is contemplated according to the inventive concepts disclosedherein.

In one example discussed in detail below, a memory structure to containa condition/action pair may include a 64-bit word-sized register (e.g.,that may be accessed and read in a single clock cycle), some number ofbits of which represent or relate to the condition 142 c to beevaluated, and another number of bits of which represent or relate tothe action 144 c to be taken if the condition is satisfied. In onenon-limiting example, the 64-bit register is segregated into threeportions, and the condition 142 c and action 144 c are encoded in thesethree different portions respectively as: 1) an “op-code” represented bya 16-bit unsigned integer; 2) a 16-bit “action parameter”; and 3) a32-bit “condition operand”, wherein the information contained in theaction parameter and the condition operand may facilitate implementationof an operation contained in the op-code. TABLE 1 below illustrates thegeneral format of such a 64-bit register, in which the op-code portionis represented in bits 48-63, the action parameter is represented inbits 32-47, and the condition operand is represented in bits 0-31.

TABLE 1 Illustrative Encoding of Condition/Action Pair 63-48 47-32 31-0Op-code Action Parameter Condition Operand

With respect to the op-code portion of the 64-bit register illustratedin TABLE 1, TABLE 2 below provides an exemplary format for differentfields of the 16-bit op-code:

TABLE 2 Illustrative Encoding of Condition/Action Op-code F E D C B A 98 7 6 5 4 3 2 1 0 OP ACT C X N S L CTRIn the example above, the four most significant bits of the op-code(bits 15-12, respectively labeled in TABLE 2 as “F”, “E”, “D”, and “C”)specify a condition type code (labeled as “OP”) for the condition 142 cto be evaluated. The four next most significant bits (bits 11-8,respectively labeled in TABLE 2 as “B”, “A”, “9”, and “8”) represent anaction operand (labeled as “ACT”) for the action 144 c. The remainingbits of the op-code include a chain bit C, an XOR bit X, a notify bit N,a satisfied bit S, a last condition bit L, and one or more countervalues CTR, each of which is described in turn in greater detail below.

In the present example, with reference again to TABLE 1, the 32-bit“condition operand” in bits 0-31 of the 64-bit register may be usedtogether with the condition type code specified in the OP field of theop-code to determine whether or not a particular condition has beensatisfied. Additionally, the 16-bit “action parameter” in bits 32-47 ofthe 64-bit register may be used together with the action operandspecified in the ACT field of the op-code to specify a correspondingaction to be taken if the particular condition is satisfied. Moreover,the op-code fields C (chain), X (XOR), and CTR (counter) may be employedfor evaluation of a particular condition, and the op-code fields N(notify), S (satisfied) and L (last condition) may be employed tospecify a corresponding action. Thus, as discussed in greater detailbelow, a first set of bits/fields of the 64-bit register shown in TABLE1, namely OP, C, X, CTR and the “condition operand,” may collectivelydefine the condition 142 c of the condition/action pair represented inthe 64-bit register; similarly, a second set of bits/fields of the64-bit register, namely ACT, N, S, L and the “action parameter,” maycollectively define the action 144 c of the condition/action pairrepresented in the 64-bit register.

More specifically, the condition type code OP of the op-code shown inTABLE 2 specifies the type of condition to be monitored, one or moreinput signals to be monitored, and/or the state of any monitored inputsignal(s) that satisfies the condition. For some condition type codesOP, satisfaction of the condition depends at least in part upon one ormore values of the 32-bit “condition operand” represented in bits 0-31of the 64-bit register (refer to TABLE 1 above). Exemplary conditiontype codes that may be present in the OP field of the op-code include,but are not limited to:

 0 - Register is Unused  1 - Act when counter # CTR is less than orequal to the operand  2 - Act when counter # CTR is greater than orequal to the operand  3 - Act when rising edge detected on any inputsset in operand[0 . . 15]  4 - Act when falling edge detected on anyinputs set in operand[0 . . 15]  5 - Act when trigger ladder fires onany ladder set in operand[0 . . 3]  6 - Act when high signal present onany inputs set in operand[0 . . 15]  7 - Act when low signal present onany inputs set in operand[0 . . 15]  8 - Act when high signal present onall inputs set in operand[0 . . 15]  9 - Act when low signal present onall inputs set in operand[0 . . 15] 10 - Act when set state exists onany flags set in operand[0 . . 31] 11 - Act when clear state exists onany flags set in operand[0 . . 31] 12 - Act when set state exists on allflags set in operand[0 . . 31] 13 - Act when clear state exists on allflags set in operand[0 . . 31] 14 - Act when counter # CTR direction(condition[bit 0]: 1 −> inc, 0 −> dec) 15 - undefined

Additional condition type codes specified in the OP field of the op-codecan be defined using the X bit, discussed below (e.g., condition typecodes 3-15 above may be redefined using the X bit). In this non-limitingexample, the CTR bits are used for condition type codes 1, 2 and 14; inother examples, the CTR bits may be used to redefine the other conditiontype codes when non-zero.

The action operand ACT of the op-code shown in TABLE 2 above specifies acorresponding action to be taken when the condition specified by thecondition type code and the condition operand (and in some cases otherfields of the 64-bit register) is satisfied. For some action operandsACT, the action to be taken depends at least in part upon one or morevalues of the 16-bit “action parameter” represented in bits 32-47 of the64-bit register (refer to TABLE 1 above). Exemplary action operand codesthat may be present in the ACT field of the op-code include, but are notlimited to:

 0 - No-op - do nothing (e.g., raise interrupt completion if N is set) 1 - Queue Message Transmit The action-parameter is interpreted ascontaining the descriptor # in bits 0-3, a notify housekeeping CPU onmessage acknowledgement flag in bit 5, a notify housekeeping CPU onmessage failure flag in bit 6, a payload index in bits 12-6.  2 - Setoutputs: A bit set in the action parameter indicates the output is toset.  3 - Clear outputs: A bit set in the action parameter indicates theoutput is to cleared.  4 - Latch data inputs. (No action parameter)  5 -Latch counter value: A bit set in the action parameter indicates thecounter is to latched.  6 - Zero counter: A bit set in the actionparameter indicates the counter is to zeroed.  7 - Set flags MSW: A bitset in the action parameter indicates the flag is to be set.  8 - Setflags LSW: A bit set in the action parameter indicates the flag is to beset.  9 - Clear flags MSW: A bit set in the action parameter indicatesthe flag is to be cleared. 10 - Clear flags LSW: A bit set in the actionparameter indicates the flag is to be cleared. 11 - Get Semaphore: Thesemaphore index is given in the action parameter. 12 - ReleaseSemaphore: The semaphore index is given in the action parameter. 13 -15 - reserved. Action 15 may be an extension action with some number ofbits of the action parameter used to indicate the action with a reducednumber of bits to indicate the action operand.

The 16-bit action parameter used in conjunction with some of the actionoperands specified above may include, but is not limited to: adescriptor # (e.g., bits 0-3), a notify ack (e.g., bit 4), a notify exh(e.g., bit 5), a payload # (e.g., bits 6-12) or a bit field (e.g., bits13-15).

As described above, other bits of the 16-bit op-code contained in bits48-63 of the 64-bit register representing a condition/action pair mayinclude a chain bit C from the previous register. If the chain bit C isset, the condition 142 c in the preceding event table register 140 cmust be true before the condition 142 c in this event table register 140c can be considered. They may also include an XOR bit X that implementsa shadow register so that comparisons do not have to deal with overflowor underflow; a notify bit N, which, when set to 1, causes uponsatisfaction of the input conditions a completion message to beforwarded to the housekeeping CPU 190, and a satisfied bit S that is setwhen the condition 142 c is satisfied.

The other bits may also include a last condition bit L that is used tocause the scanner to reset the condition operand OP to zero when thecondition 142 c is satisfied. In other words, the last condition bit Lprevents the next scan from of the event table 112 re-satisfying thecondition. When multiple conditions 142 c are to be satisfied (e.g.,using the chain bit C as described below) before an action 144 c is tobe performed, the preceding registers will not have the L bit set sothat the operation can be re-evaluated. Event table registers that arechained together with a do-always condition may have the last bit set toprevent the action from recurring.

The action engine 110 c can be programmed using the SCORE™ programminglanguage. In particular, as discussed above, the housekeeping CPU(master processor) 190 may be programmed via an inventive programminglanguage according to one embodiment of the present invention that, whencompiled, enables the master processor to in turn provide instructionsto task the action engine, in the form of condition/action pairs.Examples of SCORE™ statements and resulting event table settings aregiven below. The SCORE™ statements are formatted such that each line ofSCORE™ code matches with a single condition/action pair:

wait for counter [3] >= 0x1000 from 0x10000 and for set flag 4 senddescriptor[1] with payload[2] set output 0 ---- OP ACT C X N S L CTR APOPERAND 2 0 0 1 0 0 0 3 0x0000 0x00101000 # xor ctr value 10  1 1 0 0 01 0 0x00B1 0x00000010 # notify ack/exh = 1 2 2 1 0 1 0 1 0 0x00010x00000000 # ctr[0] >= 0 (always true) - ==== wait for rising edge ofinput 0 and for clear inputs 1 and 2 latch counter[2] set outputs 3 and4 ---- OP ACT C X N S L CTR AP OPERAND 3 0 0 0 0 0 0 0 0x0000 0x00000001# note we never set the S bit 9 5 1 0 0 0 1 0 0x0004 0x00000006 2 2 1 01 0 1 0 0x0018 0x00000000 - ==== wait for rising edge of input 0 and forclear inputs 1 and 2 set output 3 ---- OP ACT C X N S L CTR AP OPERAND 30 0 0 0 0 0 0 0x0000 0x00000001 9 2 1 0 1 0 1 0 0x0008 0x00000006 - ====wait for rising edge of input 0 set output 3 ---- OP ACT C X N S L CTRAP OPERAND 3 2 0 0 1 0 1 0 0x0008 0x00000001 - ==== wait forcounter[3] >= 0x1100 from 0x10203040 and for set input 1 or 2 senddescriptor[2] set output 4 ---- OP ACT C X N S L CTR AP OPERAND 2 0 0 00 0 0 3 0x0000 0x10204140 # no xor 6 1 1 0 0 0 1 0 0x1FF2 0x00000010 #AP[12:6] = no payload 2 2 1 0 1 0 1 0 0x0010 0x00000000 # op = ctr[0] >=0 OP, C, X, CTR and OPERAND define the condition. ACT, N, S, L and APdefine the action.

Chain Bits for Monitoring More Complex Conditions

In some cases, the registers 140 c of the event table 112 shown in FIG.6 may not be wide enough to describe more complex condition/actionpairs. In such cases, the action engine 110 c, event table 112, andscanner 130 c can be configured to evaluate more complicated sets ofinput conditions (e.g., multiple conditions upon satisfaction of whichone or more actions are predicated) using chain bits (denoted “C” inFIG. 6). Each chain bit is logically part of the corresponding set ofconditions 142 c in that it includes the satisfaction of a particularcondition 142 c represented in the previous event table register 140 c.In effect, chain bits can be used to increase the effective (and finite)size of a single event table register 140 c by linking a group ofcontiguous event table registers 140 c to form a single “super register”for the purposes of defining groups of input conditions, all of whichmust be satisfied for the actions described in this chained group ofevent table entries to be taken. Chaining together contiguous blocks ofevent table registers 140 c logically “ANDs” the chained registers 140 ctogether, i.e., it causes them to react to a particular combination ofinput signals 66 by issuing a particular set of instructions (possiblyin a predetermined order).

FIG. 8 illustrates how chained event table registers 140 c identify andreact to a group of conditions 142 c that have been chained together.(For simplicity, FIG. 8 shows only the sets of conditions 142 c andoutputs 144 c for each register 140 c.) Each event table register 140 creacts to a different combination of sensor inputs A-C and currentcounter values CTR (not shown in FIG. 8) as well as flag register valuesand whether a semaphore request earlier in the set of chained eventtable registers was successful. By convention, the first event tableentry in a chained group 140 c-1 will not have its chain bit set. Inthis example, event table registers 140 c-2 through 140 c-4 all havechain bits C set to 1. Event table register 140 c-5 has a low chain bitC and therefore operates independently of event table registers 140 c-1through 140 c-4.

Chained registers 140 c-1 and 140 c-2 each include a respectivecondition 142 c-1 and 142 c-2 and a do-nothing (no-op) action 144 c-1and 144 c-2, followed by a “critical register”—here, a single register140 c-3 with both a “useful” condition 142 c-3 and an action 144 c-3other than a no-op. Such a “critical register” may be, and in this caseis, followed by another register 140 c-4 with an additional action whichshould also be taken when the chained group's input conditions are met.To ensure that the useful action 144 c-4 is also immediately taken whenthat of the critical entry is executed, the input condition 142 c-4 isset to a condition that is tautologically true i.e. counter[0]>=0 (noXOR). This will not cause premature execution of the action in thisevent table entry since as part of a chained group of event tableentries, all of the preceding input conditions in this chained groupmust also be satisfied. The last condition bit L is set in register 140c-2, which means that registers 140 c-1 and 140 c-2 must be satisfied ina single table scan before the satisfied bit S is set on the criticalregister 140 c-3. Once the satisfied bit S is set on the criticalregister 140 c-3, the state of the preceding registers 140 c-1 and 140c-2 does not matter as the action 144 c-4 in the critical register 140c-4 will be retried on every scan (assuming it was a semaphore or sendaction, as all other actions complete on the first attempt). Theregister 140 c-4 in the chain after the critical register 144 c-3 willhave the last condition bit L set, indicating the satisfied bit S can beset by the scanner 130 c.

Semaphores for Tracking Evolutions of a Dynamic Environment

The action engine 110 c shown in FIG. 6 can also issue a series ofinstructions in response to an evolution of the real-world system. Forevolutions that occur more slowly than the maximum CPU response time(e.g. 10 to 1000 μs), the scanner 130 c may report matches (satisfiedconditions) to the housekeeping CPU 190, which responds by issuinginstructions and/or updating one or more of the event table registers140 c as described above. For faster evolutions (i.e., those that mayoccur more quickly than the maximum CPU response time), the actionengine 110 c may use one or more semaphores to make conditions 142 ccontingent upon each other and/or to prevent contention (collision)among different registers 140 c whose respective conditions 142 c are atleast partially satisfied by the same input signal(s) 66 withoutintervention by the housekeeping CPU 190. Generally speaking, semaphoresfacilitate management of resource contention, and may be acquired andreleased by the action engine to ensure availability one or moreresources on which evaluation of one or more conditions rely.

In some instances, an event table register 140 c-1 in a chained group ofevent table registers 140 c may attempt to acquire one of a collectionof semaphores which are managed by the scanner but which will typicallybe released by the scanner in response to semaphore release action in alater event table entry or may be released unilaterally by thehousekeeping CPU 190. Together with their other input conditions,successful acquisition of the semaphore will automatically be anecessary condition for the execution of any subsequent response actionspresent in such a chained collection of event table registers.

In illustrative embodiments, semaphore handling is based on atest-and-set operation. A semaphore can be considered to be an R/Sflip-flop. A set operation involves reading the output Q of the flopsimultaneously with clocking the S input of the R/S flip-flop. If thesemaphore was previously unset (result of the simultaneous read of theoutput of the R/S flip-flop was a logic low), then the set action isconsidered to be completed. If the semaphore was previously set, thenthe set action is not considered to be successful and actions dependenton a successful semaphore set will not be taken. Unlike other actions,the semaphore get action causes any subsequent registers 140 c in thischain to be ignored until the semaphore get is successful (on a futurescan). A release of the semaphore is accomplished by clocking the Rinput to the flop. Arbitrated versions of these semaphores may be usedto coordinate the operation of multiple event table scanners 130 c(e.g., as described with respect to FIG. 9). For example, an actionengine with multiple scanners 130 c may use a simple round robinarbitration scheme.

To see how the event table 112 uses semaphores, consider threeconcurrent processes that are involved in setting a clocked output(clock on output 0, data on outputs 1-7): (a) a first processresponsible for waiting for a triggering event, acquiring a semaphore,setting the clock output low, setting the output value on 1-7, andenabling the second & third processes; (b) a second process thatincludes waiting for the setup time, setting the clock output high, andenabling the third process; and (c) a third process that includeswaiting for the combined setup and hold times, releasing the semaphore,and notifying the housekeeping CPU 190. Each of the three processes isrepresented by a group of chained registers 140 c in the event table112. (The semaphore may be used by any process wanting to manipulateoutputs 0-7, counter[1] and flag[0], allowing multiple sets of theseprocesses on the event table 112 to send a clocked output withoutinterfering with one another.) Assume further that the countercounter[1] has been set up to count microsecond ticks and is used fortiming the output signals. In this example, the setup and hold time areboth 1 ms on the output signals.

To begin, the first process acquires a semaphore. Once it has acquiredthe semaphore, it clears outputs 0 and 2-7, sets output 1, resets acounter (counter[1]) configured to count timebase pulses, in this case a1 MHz timebase, and sets a flag (flag[0]) using a series of fiveregisters that are chained together. The first process may be expressedusing the following SCORE™ statements (with comments) andcondition/action pairs (coded as above and in hexadecimal format):

wait for rising edge of input 9 get semaphore[0] clear outputs 0, 2, 3,4, 5, 6, 7 # these chained action are set output 1 # deferred until thescan in which reset counter[1] # semaphore 0 acquisition succeeds setflag[0] - --- OP ACT C X N S L CTR AP OPERAND 3 11  0 0 0 0 1 0 0x00000x00000200 # on rising edge, get semaphore 2 3 1 0 0 0 1 0 0x00FD0x00000000 # then, clear outputs 0, 2-7 2 2 1 0 0 0 1 0 0x00020x00000000 # then, set output 1 2 6 1 0 0 0 1 0 0x0002 0x00000000 #then, reset counter[1] 2 8 1 0 1 0 1 0 0x0001 0x00000000 # then, setflag[0] - --- - 0x3B08_0000 0x0000_0200 # restatement of thecondition/action pairs - 0x2388_00FD 0x0000_0000 # given above inhexadecimal format - 0x2288_0002 0x0000_0000 - 0x2688_0002 0x0000_0000 -0x28A8_0001 0x0000_0000

The second process begins once the flag is set. It then sets an outputat a given counter value. The corresponding SCORE™ statements (withcomments) and condition/action pairs (coded as above and in hexadecimalformat) for the second process are:

wait for flag[0] and for counter [1] >= 1000 set output 0 --- OP ACT C XN S L CTR AP OPERAND 12 0 0 0 0 0 0 0 0x0000 0x00000001 # wait onflag[0] 2 2 1 0 1 0 1 1 0x0001 0x000003e8 # ctr[1] >= 1000, set output--- 0xC000_0000 0x0000_0001 0x22A9_0001 0x0000_03e8

The third process begins once the flag is set. Once the given counterreaches a second value, it clears the first flag and releases thesemaphore. The corresponding SCORE™ statements (with comments) andcondition/action pairs (coded as above and in hexadecimal format) forthe third process are:

wait for flag[2] and for counter[1] >= 2000 clear flag[0] and flag[1]release semaphore[0] --- OP ACT C X N S L CTR AP OPERAND 12   0 0 0 0 00 0 0x0000 0x00000002 # wait on flag[1] 2 10 1 0 0 0 1 1 0x00010x000007D0 # ctr[1] >= 2000, clear flag[0] 2 12 1 0 1 0 1 0 0x00000x00000000 # ctr[0] >= 0, rel semaphore[0] --- 0xC000_0000 0x0000_00020x2A89_0001 0x0000_07D0 0x2CA8_0000 0x0000_0000

Note that only one flag is used to enable the second and thirdprocesses, (b) and (c), because the third process, (c), is waiting onthe counter elapsing the combined setup and hold times. The semaphoreprotects the use of the counter and the flag so that all groups ofprocesses can use the same counter and flag.

Alternatively, these three separate, concurrently running processes maywritten as a single SCORE™ statement because the timing requirements ofthe setup-and-hold times are 1 ms, which is more than enough time forthe housekeeping CPU 190 to act:

wait for rising edge of input 9 get semaphore[0] clear outputs 0, 2, 3,4, 5, 6, 7 set output 1 reset counter[1] wait for counter[1] >= 1000 setoutput 0 wait for counter[1] >= 2000 release semaphore[0]

The housekeeping CPU 190 may replace the first four-register chain witha single-register chain on completion. On the completion of that secondchain, another single chain entry would be written to execute the thirdwait and the semaphore release.

Action Engines with Multiple Event Table/Scanner Co-Processors

FIG. 9 shows an action engine 110 c that includes multiple parallelco-processors (respectively, co-processors 120 c-1 through 120 c-n;collectively, co-processors 120 c) coupled to an input bus 102 via arespective input port (respectively input ports 158 c-1 through 158 c-n;collectively input ports 158 c). Each co-processor 120 c includes arespective event table (respectively event tables 110 c-1 through 110c-n; collectively event tables 110 c) coupled to a respective scanner(respectively scanners 130 c-1 through 130 c-n; collectively scanners130 c). As above, each event table 112 includes multiple entries, eachof which represents one or more sets of independent conditions andcorresponding actions.

The co-processors 120 c operate in parallel to execute thecondition/action pairs stored in the event tables 110 c with very lowlatency, e.g., latencies of about 1.6 μs or less. During parallelexecution, each scanner 130 c compares the conditions in the event table112 to input signals 66 received via the input bus 102 and input port158 c and executes instructions in the event of a match as describedwith respect to FIGS. 6-8. If appropriate, the scanner 130 c transmitsoutput signals 68 via a respective output port (respectively outputports 160 c-1 through 160 c-n; collectively output ports 160 c) to theoutput bus 102. The action engine 110 c may also include counters, flagregisters, and/or semaphore registers as described above with respect toFIG. 6.

Examples of the action engines described above can be implemented as asingle event table scanner on a single FPGA (e.g., using HDL code) witha memory large enough to hold 144 c opcodes, or “condition/action”pairs. The scanner executes the event table by evaluating the conditionssequentially. When the scanner finds a satisfied chain of conditions, itexecutes the actions and notifies a master CPU, which may implemented onthe same FPGA, as to which register(s) in the event table is being usedfor the satisfied condition. The master CPU reloads the register(s) inquestion with new op-codes as the process follows the evolution of thereal-world condition. Alternatively, action engines may be implementedas: a dedicated chip containing event table memories and scannersembedded in a peripheral component interface (PCI) card and used in ageneral-purpose computer; an embedded processor to decode an event tableand run native instructions instead of placing native op-codes in theco-processor memory; and multiple FPGAs, each of which has a separateFPGA program to evaluate the conditions at a very low latency.

Dynamic Environments Employing Machine Vision Techniques/Equipment

As noted earlier, control systems according to various embodiments ofthe present invention, as well as constituent elements thereof, may havewide applicability for monitoring and/or controlling a variety ofdynamic environments, particularly those requiring low latency (i.e.,significantly fast response time) and/or low variability latency. Oneexemplary application of control systems according to the presentinvention is given by a dynamic environment in which machine visiontechniques and/or equipment are employed.

FIG. 10 is a block diagram of a dynamic environment in which machinevision techniques and equipment are used, together with a control systemaccording to embodiments of the present invention for monitoring andcontrolling the dynamic environment. The dynamic environment illustratedin FIG. 10 generally relates to an automated process 10, in whichvarious robotics equipment 22 as well as machine vision equipment(collectively equipment 20) may be employed to facilitate implementationof the automated process 10, wherein the machine vision equipment mayinclude one or more image acquisition devices 42 and lighting equipment44. Examples of an automated process 10 for which the control conceptsdiscussed herein are applicable include, but are not limited to,counting, tracking, sorting and/or handling of parts on an assembly line(e.g., for automotive, consumer goods manufacturing and/or agriculturalapplications), quality control functions (e.g., automated inspection fordefects) in connection with a manufacturing process, measurement ofposition and/or orientation of parts for manipulation by roboticsequipment, and removing undesirable artifacts from bulk materials (e.g.,food stuffs, agricultural products, etc.).

In FIG. 10, the dynamic environment also includes various actuators orcontrol devices 30 (in a manner similar to that shown in FIG. 1) tocontrol the robotics equipment 22, the lighting equipment 24 and/or theimage acquisition device(s) 42. The environment also includes varioussensors or input devices 40 to monitor the automated process 10 andprovide information (e.g., one or more input signals 66) representing amonitored condition of the environment at a given time. As shown in FIG.10, the sensors may include the one or more image acquisition devices 42to acquire images relating to the automated process, as well as one ormore other sensors 44 (e.g., temperature, humidity, pressure, lightand/or other environmental sensors; counters; receive queues forinformation packets, some of which information packets may be providedby one or more image acquisition devices or other devices, etc.), forproviding input signals representing monitored conditions.

FIG. 10 also shows a control system 100, including a master processor190 and an action engine 110 as described above in connection withvarious embodiments, to receive and process one or more input signals 66representing monitored conditions as a function of time so as to provideone or more output signals 68 to the control devices 30 (which in turncontrol one or more of the robotics equipment, the lighting equipment,and the image acquisition devices). Additionally, the dynamicenvironment shown in FIG. 10 also may include an image processingcomputer 200, communicatively coupled to the control system 100, toprocess image information acquired by the one or more image acquisitiondevices and to control the lighting equipment. In embodiments includingthe image processing computer 200, at least some of the informationotherwise provided by the one or more input signals 66 representingmonitored conditions of the dynamic environment may be provided by theimage processing computer 200 to the control system 100, particularly inconnection with information derived from images acquired by the one ormore image acquisition devices.

In the dynamic environment shown in FIG. 10, the image acquisitiondevice(s) 42 and the lighting equipment 24 may be particularly employedto implement machine vision techniques in connection with monitoring andcontrol of the automated process 10. The term “machine vision” verygenerally refers to analysis of images to extract data for purposes ofcontrolling a process. Machine vision techniques typically comprise asequence of operations involving acquisition of images using any of avariety of image acquisition devices (e.g., digital still or videocameras), and in some cases lenses and various lighting equipment (whichin some instances may be particularly designed and configured to providevarious differentiation of certain objects from the general environmentto facilitate subsequent image processing). Image data provided by oneor more image acquisition devices can be in a variety of formats (e.g.,video sequences, views from multiple cameras, or multi-dimensional data,as from a medical scanner). Acquired images are then processed (e.g.,via execution of various image processing software by an imagingprocessing computer 200 operably coupled to the machine vision equipment20 and the control system 100, and/or one or more otherindependent/external computing devices) so as to extract variousinformation from the images, which extracted information then is used tomake decisions in connection with controlling the automated process.

With respect to various lighting equipment and techniques that may beemployed for machine vision, two-dimensional visible light imagingtechniques (using monochromatic or color light sources) perhaps are mostcommonly adopted. However, other suitable imaging techniques include,but are not limited to, selective infrared imaging in which infraredlighting equipment (e.g., sources and/or filters) may be employed, linescan imaging, three-dimensional imaging of surfaces, and X-ray imaging.Regarding the image acquisition devices, a number of form factors,functionalities, and communication protocols may be employed in suchdevices; for example, in some instances an image acquisition device maynot have any particular image processing capability, while in otherinstances image acquisition devices may be implemented with some degreeof image processing functionality (e.g., “smart” cameras or sensors).Also, various commercially available image acquisition devices may beconfigured to communicate data via any of a variety of interfaces, suchas Ethernet, USB or FireWire connections.

Regarding exemplary image processing techniques that may be implementedby the master processor 190 of the control system 100, the imageprocessing computer 200, and/or one or more other computing/processingdevices, examples of typical techniques include, but are not limited to,thresholding (converting a grayscale image to black and white, or usingseparation based on a grayscale value), segmentation, blob extraction,pattern recognition, barcode and data matrix code reading, opticalcharacter recognition, gauging (measuring object dimensions),positioning, edge detection, color analysis, filtering (e.g.morphological filtering) and template matching (finding, matching,and/or counting specific patterns).

In FIG. 10, various image information extracted from acquired images asa result of using any one or more of the image processing techniquesnoted above may be included as part of the overall informationrepresented by one or more input signals 66 received by the controlsystem 100 from one or more sensors/input devices, and/or provided tothe control system 100 by the image processing computer 200. Forexample, such extracted image information may indicate that a particularobject (e.g., a part on an assembly line) was present in one or moreimages acquired at a particular time, that a particular position and/ororientation of an object was detected in one or more images, that aparticular defect was observed in an object present in one or moreimages, and the like. Such information extracted from images may be usedalone or in combination with other information from one or more sensorsto represent a monitored condition of the automated process at a giventime, upon which the control system may be configured to prescribe oneor more particular corresponding actions to be taken in connection withthe automated process 10.

CONCLUSION

While various inventive embodiments have been described and illustratedherein, those of ordinary skill in the art will readily envision avariety of other means and/or structures for performing the functionsand/or obtaining the results and/or one or more of the advantagesdescribed herein, and each of such variations and/or modifications, isdeemed to be within the scope of the inventive embodiments describedherein. More generally, those skilled in the art will readily appreciatethat all parameters, dimensions, materials, and configurations describedherein are meant to be exemplary and that the actual parameters,dimensions, materials, and/or configurations will depend upon thespecific application or applications for which the inventive teachingsis/are used. Those skilled in the art will recognize, or be able toascertain using no more than routine experimentation, many equivalentsto the specific inventive embodiments described herein. It is,therefore, to be understood that the foregoing embodiments are presentedby way of example only and that, within the scope of the appended claimsand equivalents thereto, inventive embodiments may be practicedotherwise than as specifically described and claimed. Inventiveembodiments of the present disclosure are directed to each individualfeature, system, article, material, kit, and/or method described herein.In addition, any combination of two or more such features, systems,articles, materials, kits, and/or methods, if such features, systems,articles, materials, kits, and/or methods are not mutually inconsistent,is included within the inventive scope of the present disclosure.

The above-described embodiments can be implemented in any of numerousways. For example, the embodiments may be implemented using hardware,software or a combination thereof. When implemented in software, thesoftware code can be executed on any suitable processor or collection ofprocessors, whether provided in a single computer or distributed amongmultiple computers.

Further, it should be appreciated that a computer may be embodied in anyof a number of forms, such as a rack-mounted computer, a desktopcomputer, a laptop computer, or a tablet computer. Additionally, acomputer may be embedded in a device not generally regarded as acomputer but with suitable processing capabilities, including a PersonalDigital Assistant (PDA), a smart phone or any other suitable portable orfixed electronic device.

Also, a computer may have one or more input and output devices. Thesedevices can be used, among other things, to present a user interface.Examples of output devices that can be used to provide a user interfaceinclude printers or display screens for visual presentation of outputand speakers or other sound generating devices for audible presentationof output. Examples of input devices that can be used for a userinterface include keyboards, and pointing devices, such as mice, touchpads, and digitizing tablets. As another example, a computer may receiveinput information through speech recognition or in other audible format.

Such computers may be interconnected by one or more networks in anysuitable form, including a local area network or a wide area network,such as an enterprise network, and intelligent network (IN) or theInternet. Such networks may be based on any suitable technology and mayoperate according to any suitable protocol and may include wirelessnetworks, wired networks or fiber optic networks.

The various methods or processes outlined herein may be coded assoftware that is executable on one or more processors that employ anyone of a variety of operating systems or platforms. Additionally, suchsoftware may be written using any of a number of suitable programminglanguages and/or programming or scripting tools, and also may becompiled as executable machine language code or intermediate code thatis executed on a framework or virtual machine.

In this respect, various inventive concepts may be embodied as acomputer readable storage medium (or multiple computer readable storagemedia) (e.g., a computer memory, one or more floppy discs, compactdiscs, optical discs, magnetic tapes, flash memories, circuitconfigurations in Field Programmable Gate Arrays or other semiconductordevices, or other non-transitory medium or tangible computer storagemedium) encoded with one or more programs that, when executed on one ormore computers or other processors, perform methods that implement thevarious embodiments of the invention discussed above. The computerreadable medium or media can be transportable, such that the program orprograms stored thereon can be loaded onto one or more differentcomputers or other processors to implement various aspects of thepresent invention as discussed above.

The terms “program” or “software” are used herein in a generic sense torefer to any type of computer code or set of computer-executableinstructions that can be employed to program a computer or otherprocessor to implement various aspects of embodiments as discussedabove. Additionally, it should be appreciated that according to oneaspect, one or more computer programs that when executed perform methodsof the present invention need not reside on a single computer orprocessor, but may be distributed in a modular fashion amongst a numberof different computers or processors to implement various aspects of thepresent invention.

Computer-executable instructions may be in many forms, such as programmodules, executed by one or more computers or other devices. Generally,program modules include routines, programs, objects, components, datastructures, etc. that perform particular tasks or implement particularabstract data types. Typically the functionality of the program modulesmay be combined or distributed as desired in various embodiments.

Also, data structures may be stored in computer-readable media in anysuitable form. For simplicity of illustration, data structures may beshown to have fields that are related through location in the datastructure. Such relationships may likewise be achieved by assigningstorage for the fields with locations in a computer-readable medium thatconvey relationship between the fields. However, any suitable mechanismmay be used to establish a relationship between information in fields ofa data structure, including through the use of pointers, tags or othermechanisms that establish relationship between data elements.

Also, various inventive concepts may be embodied as one or more methods,of which an example has been provided. The acts performed as part of themethod may be ordered in any suitable way. Accordingly, embodiments maybe constructed in which acts are performed in an order different thanillustrated, which may include performing some acts simultaneously, eventhough shown as sequential acts in illustrative embodiments.

All definitions, as defined and used herein, should be understood tocontrol over dictionary definitions, definitions in documentsincorporated by reference, and/or ordinary meanings of the definedterms.

The indefinite articles “a” and “an,” as used herein in thespecification and in the claims, unless clearly indicated to thecontrary, should be understood to mean “at least one.”

The phrase “and/or,” as used herein in the specification and in theclaims, should be understood to mean “either or both” of the elements soconjoined, i.e., elements that are conjunctively present in some casesand disjunctively present in other cases. Multiple elements listed with“and/or” should be construed in the same fashion, i.e., “one or more” ofthe elements so conjoined. Other elements may optionally be presentother than the elements specifically identified by the “and/or” clause,whether related or unrelated to those elements specifically identified.Thus, as a non-limiting example, a reference to “A and/or B”, when usedin conjunction with open-ended language such as “comprising” can refer,in one embodiment, to A only (optionally including elements other thanB); in another embodiment, to B only (optionally including elementsother than A); in yet another embodiment, to both A and B (optionallyincluding other elements); etc.

As used herein in the specification and in the claims, “or” should beunderstood to have the same meaning as “and/or” as defined above. Forexample, when separating items in a list, “or” or “and/or” shall beinterpreted as being inclusive, i.e., the inclusion of at least one, butalso including more than one, of a number or list of elements, and,optionally, additional unlisted items. Only terms clearly indicated tothe contrary, such as “only one of” or “exactly one of,” or, when usedin the claims, “consisting of,” will refer to the inclusion of exactlyone element of a number or list of elements. In general, the term “or”as used herein shall only be interpreted as indicating exclusivealternatives (i.e. “one or the other but not both”) when preceded byterms of exclusivity, such as “either,” “one of,” “only one of,” or“exactly one of” “Consisting essentially of,” when used in the claims,shall have its ordinary meaning as used in the field of patent law.

As used herein in the specification and in the claims, the phrase “atleast one,” in reference to a list of one or more elements, should beunderstood to mean at least one element selected from any one or more ofthe elements in the list of elements, but not necessarily including atleast one of each and every element specifically listed within the listof elements and not excluding any combinations of elements in the listof elements. This definition also allows that elements may optionally bepresent other than the elements specifically identified within the listof elements to which the phrase “at least one” refers, whether relatedor unrelated to those elements specifically identified. Thus, as anon-limiting example, “at least one of A and B” (or, equivalently, “atleast one of A or B,” or, equivalently “at least one of A and/or B”) canrefer, in one embodiment, to at least one, optionally including morethan one, A, with no B present (and optionally including elements otherthan B); in another embodiment, to at least one, optionally includingmore than one, B, with no A present (and optionally including elementsother than A); in yet another embodiment, to at least one, optionallyincluding more than one, A, and at least one, optionally including morethan one, B (and optionally including other elements); etc.

In the claims, as well as in the specification above, all transitionalphrases such as “comprising,” “including,” “carrying,” “having,”“containing,” “involving,” “holding,” “composed of,” and the like are tobe understood to be open-ended, i.e., to mean including but not limitedto. Only the transitional phrases “consisting of” and “consistingessentially of” shall be closed or semi-closed transitional phrases,respectively, as set forth in the United States Patent Office Manual ofPatent Examining Procedures, Section 2111.03.

The invention claimed is:
 1. An action engine to evaluate a plurality ofconditions of a dynamic environment, the action engine comprising: amemory to store at least one event table, the at least one event tablebeing structured as a plurality of successive contiguous memorylocations, wherein each memory location of the plurality of successivecontiguous memory locations is configured to store contents representinga particular condition of the plurality of conditions to be evaluated bythe action engine and a corresponding action to be taken if theparticular condition is satisfied; and at least one scanner,communicatively coupled to the memory so as to access the at least oneevent table, the at least one scanner comprising processing circuitryconfigured to: sequentially process the contents of the respectivememory locations of the at least one event table to evaluate theplurality of conditions represented in the contents; generate anotification signal for each condition of the plurality of conditionsthat is satisfied upon evaluation; and generate control informationrepresenting at least one action to be taken in the dynamic environmentif any of the plurality of conditions is satisfied upon evaluation. 2.The action engine of claim 1, wherein: A) the dynamic environmentincludes: A1) equipment to implement an automated process; A2) at leastone control device to control the equipment in response to at least onecontrol signal; and A3) at least one sensor to monitor the automatedprocess and generate at least one input signal representing a monitoredcondition of the plurality of conditions; and B) the at least onescanner of the action engine: B1) receives the at least one input signalrepresenting the monitored condition; B2) processes the at least oneinput signal so as to determine if at least a first conditionrepresented by the contents of at least a first memory location of theevent table is satisfied; and B3) provides at least first controlinformation representing at least one first action to be takencorresponding to the at least one first condition if the monitoredcondition matches the at least one first condition.
 3. A control system,comprising: the action engine of claim 2; and a master processorcommunicatively coupled to the action engine, the master processorconfigured to, upon execution of processor-executable instructionsstored in the master processor: provide to the action engine thecontents of the respective memory locations of the at least one eventtable; and receive from the action engine a notification signal for eachcondition of the plurality of conditions that is satisfied uponevaluation.
 4. A machine vision system, comprising: the action engine ofclaim 2; the equipment to implement the automated process in A1); the atleast one control device in A2) to control the equipment; and the atleast one sensor to monitor the automated process, wherein: theequipment to implement the automated process comprises: roboticsequipment; and lighting equipment to provide controlled ambient lightingfor the automated process; the at least one control device includes aplurality of actuators coupled to the robotics equipment and/or thelighting equipment to control the robotics equipment and/or the lightingequipment; the at least one sensor comprises at least one imageacquisition device to acquire at least one image of at least a portionof the automated process; and the action engine is communicativelycoupled to the at least one control device and the at least one sensor,to receive the at least one input signal generated by the at least onesensor and to control the plurality of actuators and/or the at least oneimage acquisition device based at least in part on at least the firstcontrol information generated in B3).
 5. The action engine of claim 1,further comprising: at least one input interface, communicativelycoupled to the at least one scanner, to receive at least one inputsignal representing a monitored condition of the plurality of conditionsof the dynamic environment, wherein: the processing circuitry of the atleast one scanner compares a value of the at least one input signal toat least a first portion of the contents of at least one memory locationof the at least one event table, wherein the first portion of thecontents of each memory location represents the particular condition tobe evaluated; and if the value of the at least one input signal matchesat least the first portion of the contents of the at least one memorylocation and representing the particular condition to be evaluated, theprocessing circuitry of the at least one scanner processes a secondportion of the contents of the at least one memory location representingthe corresponding action to be taken in the dynamic environment so as toprovide at least some of the control information.
 6. The action engineof claim 5, wherein: the at least one event table includes a fixedmaximum number of successive contiguous memory locations; and themaximum number of memory locations is based at least in part on amaximum permissible latency defined by a required response time forproviding the control information in the dynamic environment if anycondition of the plurality of conditions is satisfied.
 7. The actionengine of claim 5, wherein the processing circuitry of the scannercomprises: comparator logic circuitry to compare the value of the atleast one input signal to at least the first portion of the contents ofthe at least one memory location; action logic circuitry to process thesecond portion of the contents of the at least one memory location andrepresenting the corresponding action to be taken, and provide the atleast some of the control information; sequencing logic circuitry tocontrol the at least one event table so as to sequentially provide thecontents of the respective memory locations to the comparator logiccircuitry and the action logic circuitry; and event table writearbitration logic circuitry to control the at least one event table soas to write new contents to at least one memory register of the at leastone event table.
 8. The action engine of claim 5, wherein: the contentsof each memory location of the plurality of successive contiguous memorylocations includes a condition/action pair, the condition/action pairincluding a first number of bits constituting the first portion andhaving respective values representing a particular condition of theplurality of conditions to be evaluated, and a second number of bitsconstituting the second portion and having respective valuesrepresenting the corresponding action to be taken if the particularcondition is satisfied; and the processing circuitry of the scannercomprises: a comparator coupled to the at least one memory location tocompare the respective values of the first number of bits representingthe particular condition and the value of the at least one input signalrepresenting the monitored condition of the plurality of conditions, thecomparator further configured to generate a match signal if theparticular condition matches the monitored condition; and a gate,coupled to the at least one memory location and coupled to thecomparator so as to receive the match signal, to output the secondnumber of bits having respective values representing the correspondingaction to be taken if the match signal is asserted by the comparator. 9.The action engine of claim 5, further comprising at least one semaphoreregister, communicatively coupled to the at least one scanner, to storeat least one semaphore, wherein: the at least one semaphore facilitatesmanagement of resource contention; and the at least one scanner acquiresand releases the at least one semaphore to ensure availability of atleast one resource on which evaluation of at least one condition of theplurality of conditions relies.
 10. The action engine of claim 5,wherein: the at least one input signal includes a plurality of inputsignals, wherein respective values of the plurality of input signals ata given time represent the monitored condition of the plurality ofconditions; and the at least one input interface is configured toreceive the plurality of input signals.
 11. The action engine of claim10, wherein the respective values of the plurality of input signalscomprise at least one of: a plurality of real-time values representingthe monitored condition; a plurality of latched values representing themonitored condition; at least one multi-bit digital value representingthe monitored condition; a plurality of binary values respectivelyrepresenting different sensed parameters constituting the monitoredcondition; and at least one binary value representing at least onesemaphore.
 12. The action engine of claim 5, wherein the at least oneinput interface further is configured to receive the contents of eachmemory location of the event table from an external device that receivesthe notification signal generated by the processing circuitry of the atleast one scanner.
 13. The action engine of claim 5, further comprising:at least one output interface, communicatively coupled to the at leastone scanner, to provide the notification signal for each condition ofthe plurality of conditions that is satisfied upon evaluation, and tofurther provide the at least some of the control information based atleast in part on the second portion of the contents of the at least onememory location representing the corresponding action to be taken in thedynamic environment.
 14. The action engine of claim 13, wherein thecorresponding action to be taken in the dynamic environment, asrepresented by the at least some of the control information, includes atleast one of: sending at least one data packet to at least one controldevice in the dynamic environment; setting and/or clearing at least oneflag bit; setting and/or clearing at least one output bit; settingand/or clearing at least one semaphore; and latching and/or resetting atleast one counter.
 15. The action engine of claim 5, wherein: eachmemory location of the at least one event table includes at least onememory register having a first number of bits; and the first portion ofthe contents of each memory location representing the particularcondition to be evaluated includes a second number of bits smaller thanthe first number, wherein at least some of the second number of bits arenonadjacent bits in the at least one memory register.
 16. The actionengine of claim 15, wherein: the second portion of the contents of eachmemory location representing the corresponding action to be taken in thedynamic environment includes a third number of bits smaller than thefirst number, wherein at least some of the third number of bits arenonadjacent bits in the at least one memory register.
 17. The actionengine of claim 5, wherein: the first portion of the contents of a firstmemory location of the plurality of successive contiguous memorylocations includes a chain bit to link the first memory location to anext memory location of the plurality of successive contiguous memorylocations, the first portion of the contents of the first memorylocation representing a first condition to be evaluated; the secondportion of the contents of the first memory location representing afirst corresponding action to be taken in the dynamic environmentincludes a first action operand indicating that no action is to be takenin the dynamic environment; the first portion of the contents of thenext memory location represents a second condition to be evaluated; andthe second portion of the contents of the next memory location includesa second action operand representing at least one action to be taken inthe dynamic environment if both the first condition and the secondcondition are satisfied.
 18. The action engine of claim 5, wherein: eachmemory location of the at least one event table includes at least onememory register having a first number of bits; the first number of bitsare partitioned as an op-code, an action parameter, and a conditionoperand; and the op-code comprises at least a condition type code and anaction operand, wherein: the condition type code and the conditionoperand constitute at least part of the first portion of the contents ofeach memory location representing the particular condition to beevaluated; and the action operand and the action parameter constitute atleast part of the second portion of the contents of each memory locationrepresenting the corresponding action to be taken in the dynamicenvironment.
 19. The action engine of claim 18, wherein: the firstnumber of bits for the at least one memory register is 64 bits; theop-code is 16 bits; the action parameter is 16 bits; and the conditionoperand is 32 bits.
 20. The action engine of claim 19, wherein the atleast one event table includes 128 memory locations.
 21. The actionengine of claim 18, wherein the op-code further comprises: a counterfield; and at least one bit relating to processing of the condition typecode.
 22. The action engine of claim 21, wherein the at least one bitrelating to processing of the condition type code includes at least oneof: a chain bit; an XOR bit; a notify bit; a satisfied bit; and a lastcondition bit.
 23. A method for evaluating a plurality of conditions ofa dynamic environment, the method comprising: A) sequentially processingcontents of respective memory locations of at least one event tablestored in a memory, the at least one event table being structured as aplurality of successive contiguous memory locations, wherein each memorylocation of the plurality of successive contiguous memory locations isconfigured to store a condition/action pair representing a particularcondition of the plurality of conditions to be evaluated and acorresponding action to be taken if the particular condition issatisfied; B) generating a notification signal for each condition of theplurality of conditions that is satisfied upon evaluation in A); and C)transmitting, to at least one control device so as to control at leastone piece of equipment in the dynamic environment, control informationrepresenting at least one action to be taken in the dynamic environmentif any of the plurality of conditions is satisfied upon evaluation inA).
 24. The method of claim 23, wherein A) comprises: A1) receiving atleast one input signal representing a monitored condition of theplurality of conditions of the dynamic environment; A2) comparing avalue of the at least one input signal to at least a first portion ofthe contents of at least one memory location of the at least one eventtable, wherein the first portion of the contents of each memory locationrepresents the particular condition to be evaluated; and A3) if thevalue of the at least one input signal matches at least the firstportion of the contents of the at least one memory location andrepresenting the particular condition to be evaluated, processing asecond portion of the contents of the at least one memory locationrepresenting the corresponding action to be taken in the dynamicenvironment so as to provide at least a portion of the controlinformation transmitted in C).
 25. The method of claim 24, wherein A3)further comprises: acquiring and/or releasing at least one semaphore tofacilitate processing of the second portion of the contents of the atleast one memory location representing the corresponding action to betaken in the dynamic environment.
 26. The method of claim 24, wherein:the at least one input signal includes a plurality of input signals,wherein respective values of the plurality of input signals at a giventime represent the monitored condition of the plurality of conditions.27. The method of claim 26, wherein the respective values of theplurality of input signals comprise at least one of: a plurality ofreal-time values representing the monitored condition; a plurality oflatched values representing the monitored condition; at least onemulti-bit digital value representing the monitored condition; aplurality of binary values respectively representing different sensedparameters constituting the monitored condition; and at least one binaryvalue representing at least one semaphore.
 28. The method of claim 23,further comprising: receiving the contents of each memory location ofthe event table from an external device that receives the notificationsignal generated in B).
 29. The method of claim 23, wherein C) comprisesat least one of: sending at least one data packet to the at least onecontrol device; setting and/or clearing at least one flag bit; settingand/or clearing at least one output bit; setting and/or clearing atleast one semaphore; and latching and/or resetting at least one counter.30. The method of claim 23, wherein: each memory location of the atleast one event table includes at least one memory register having afirst number of bits; and the first portion of the contents of eachmemory location representing the particular condition to be evaluatedincludes a second number of bits smaller than the first number, whereinat least some of the second number of bits are nonadjacent bits in theat least one memory register.
 31. The method of claim 30, wherein: thesecond portion of the contents of each memory location representing thecorresponding action to be taken in the dynamic environment includes athird number of bits smaller than the first number, wherein at leastsome of the third number of bits are nonadjacent bits in the at leastone memory register.
 32. The method of claim 24, wherein: the firstportion of the contents of a first memory location of the plurality ofsuccessive contiguous memory locations includes a chain bit to link thefirst memory location to a next memory location of the plurality ofsuccessive contiguous memory locations, the first portion of thecontents of the first memory location representing a first condition tobe evaluated; the second portion of the contents of the first memorylocation representing a first corresponding action to be taken in thedynamic environment includes a first action operand indicating that noaction is to be taken in the dynamic environment; the first portion ofthe contents of the next memory location represents a second conditionto be evaluated; and the second portion of the contents of the nextmemory location includes a second action operand representing at leastone action to be taken in the dynamic environment if both the firstcondition and the second condition are satisfied.
 33. The method ofclaim 23, wherein: each memory location of the at least one event tableincludes at least one memory register having a first number of bits; thefirst number of bits are partitioned as an op-code, an action parameter,and a condition operand; and the op-code comprises at least a conditiontype code and an action operand, wherein: the condition type code andthe condition operand constitute at least part of the first portion ofthe contents of each memory location representing the particularcondition to be evaluated; and the action operand and the actionparameter constitute at least part of the second portion of the contentsof each memory location representing the corresponding action to betaken in the dynamic environment.